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Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic

Sudhakar Jyothula (Vignan’s Institute of Engineering for Women, Visakhapatnam, India)
Sushma K. (Vignan’s Institute of Engineering for Women, Visakhapatnam, India)

Circuit World

ISSN: 0305-6120

Article publication date: 2 May 2017

84

Abstract

Purpose

The purpose of this paper is to present a single-precision floating-point multiplier where a low-power operation is attained through the reduction of switching activity. A floating-point multiplier is the basic building block for many applications such as digital signal processing (DSP) processors and multimedia applications involving a large dynamic range.

Design/methodology/approach

A floating-point multiplier was implemented in asynchronous logic such as multi-threshold null conventional logic and the proposed multi-threshold dual spacer dual rail delay insensitive logic (MTD3L). The proposed logic deals with high performance and energy efficiency.

Findings

The Institute of Electrical and Electronics Engineering (IEEE) has provided a standard to define the floating-point representation, which is known as the IEEE 754 standard. Rounding has not been implemented because it is not suitable for high-precision applications.

Originality/value

The performance aspects of the proposed asynchronous MTD3L floating-point multiplier are obtained using a Mentor Graphics tool and are compared with those of the existing asynchronous logic.

Keywords

Citation

Jyothula, S. and K., S. (2017), "Energy efficient IEEE 754 floating point multiplier using dual spacer delay insensitive logic", Circuit World, Vol. 43 No. 2, pp. 72-79. https://doi.org/10.1108/CW-03-2017-0012

Publisher

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Emerald Publishing Limited

Copyright © 2017, Emerald Publishing Limited

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