Recent progress in silicon—on—insulator (SOI) technologies has made possible the fabrication of high quality ultra—thin film structures. Preliminary research has demonstrated the advantage of fully—depleted SOI MOSFET's in term of speed and improved resistance to hot carrier degradation. The specific dual‐gate configuration of SOI transistors is schematically presented in Fig. 1(a).
Hassein—Bey, A. and Cristoloveanu, S. (1992), "SIMULATION OF INTERFACE COUPLING EFFECTS IN ULTRA—THIN SILICON ON INSULATOR MOSFET's", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 11 No. 4, pp. 513-517. https://doi.org/10.1108/eb010111Download as .RIS
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