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The purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).

In the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.

The design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.

The study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention.

The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state.

A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption.

Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

Engineers at BICC are laying the foundations for future automated cable manufacturing factories. Stephen McClelland explains its first stages—the automation of process sensing.

This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency.

The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology.

QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones.

The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.

In nano-scale-based very large scale integration technology, quantum-dot cellular automata (QCA) is considered as a strong and capable technology to replace the well-known complementary metal oxide semiconductor technology. In QCA technique, rotated majority gate (RMG) design is not explored greatly, and therefore, its advantages compared to original majority gate are unnoticed. This paper aims to provide a thorough observation at RMG gate with its capability to build robust circuits.

This paper presents a new methodology for structuring reliable 2n-bit full adder (FA) circuit design in QCA utilizing RMG. Mathematical proof is provided for RMG gate structure. A new 1-bit FA circuit design is projected here, which is constructed with RMG gate and clock-zone-based crossover approach in its configuration.

A new structure of a FA is projected in this paper. The proposed design uses only 50 number of QCA cells in its implementation with a latency of 3 clock zones. The proposed 1-bit FA design conception has been checked for its structure robustness by designing various 2, 4, 8, 16, 32 and 64-bit FA designs. The proposed FA designs save power from 46.87% to 25.55% at maximum energy dissipation of circuit level, 39.05% to 23.36% at average energy dissipation of circuit-level and 42.03% to 37.18% at average switching energy dissipation of circuit level.

This paper fulfills the gape of focused research for RMG with its detailed mathematical modeling analysis.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

This paper aims to propose a new sleep signal controlled footless domino circuit for reducing the subthreshold and gate oxide leakage currents.

In the proposed circuit, a P channel MOSFET (PMOS) sleep switch transistor is inserted between the power supply and the output node. The sleep transistor, the source of the pull-down network, and the source of the N channel MOSFET (NMOS) transistor of the output inverter are controlled by this additional sleep signal to place the footless domino circuit in a low leakage state.

The authors simulate the proposed circuit by using HSPICE in 45-nm CMOS technology for OR and AND logic gates such as OR2, OR4, OR8, AND2 and AND4 at 25°C and 110°C. The proposed circuit reduces leakage power consumption as compared to the existing circuits.

The proposed circuit significantly reduces the total leakage power consumption up to 99.41 and 99.51 per cent as compared to the standard dual-threshold voltage footless domino circuits at 25°C and 110°C, respectively, and up to 93.79 and 97.98 per cent as compared to the sleep control techniques at 25°C and 110°C, respectively. Similarly, the proposed circuit reduces the active power consumption up to 26.76 and 86.25 per cent as compared to the standard dual-threshold voltage and sleep control techniques footless domino circuits at 25°C and 110°C, respectively.

The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power.

In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size.

This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area.

To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler.

The simulation of the planned circuit with notional information established the practical identity of the scheme.

The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool.

The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.

Software tools are an essential part of any IC design system but there are dangers associated with the introduction of CAD systems. This paper attempts to lift the software cloak which, along with the ubiquitous workstation, tends to cover the finer points of CMOS design. This paper should help to make the designer or user of gate arrays more aware of the important features such as power dissipation, the use of transmission gates, latch‐up prevention, the pitfalls of using circuit simulators, and the importance of selecting the correct package.