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During the last few years an increasing number of flip‐chip (FC) interconnection technologies have emerged. While flip‐chip assembly offers many advantages compared with conventional packaging techniques, several aspects prevent this technology from entering the high volume market. Among these are the availability of bumped chips and the costs of the substrates, i.e., ceramic substrates with closely matching coefficient of thermal expansion (CTE) to the chip, in order to maintain high reliability. Only recently, with the possibility of filling the gap between chip and organic substrate with an encapsulant, was the reliability of flip‐chips mounted on organic substrates significantly enhanced. This paper presents two approaches to a fluxless process, one based on soldering techniques using Au‐Sn metallurgy and the other on adhesive joining techniques. Soldering is performed with a thermode and with a laser based system. For both of these FC‐joining processes, alternative bump mettallurgies based on electroplated gold, electroplated gold‐tin, mechanical gold and electroless nickel gold bumps are applied.

Wafer-level stencil printing of a type-6 Pb-free SAC solder paste was statistically evaluated at 200 and 150 μm pitch using three different stencil manufacturing technologies: laser cutting, DC electroforming and micro-engineered electroforming. This investigation looks at stencil differences in printability, pitch resolution, maximum achievable bump height, print co-planarity, paste release efficiency, and cleaning frequency. The paper aims to discuss these issues.

In this paper, the authors present a statistical evaluation of the impact of stencil technology on type-6 tin-silver-copper paste printing. The authors concentrate on performances at 200 and 150 μm pitch of full array patterns. Key evaluated criteria include achievable reflowed bump heights, deposit co-planarity, paste release efficiency, and frequency of stencil cleaning. Box plots were used to graphically view print performance over a range of aperture sizes for the three stencil types.

Fabrication technologies significantly affect print performance where the micro-engineered electroformed stencil produced the highest bump deposits and the lowest bump height deviation. Second in performance was the conventional electroformed, followed by the laser-cut stencil. Comparisons between the first and fifth consecutive print demonstrated no need for stencil cleaning in the case for the micro-engineered stencil for all but the smallest spacings between apertures. High paste transfer efficiencies, i.e. above 85 per cent, were achieved with the micro-engineered stencil using low aperture area ratios of 0.5.

Stencil technology influences the maximum reflowed solder bump heights achievable, and bump co-planarity. To date, no statistical analysis comparing the impact of stencil technology for wafer-level bumping has been carried out for pitches of 200 μm and below. This paper gives new insight into how stencil technology impacts the print performance for fine pitch stencil printing. The volume of data collected for this investigation enabled detailed insight into the limitations of the printing process and as a result for suitable design guidelines to be developed. The finding also shows that the accepted industry guidelines on stencil design developed by the surface mount industry can be broken if the correct stencil technology is selected, thereby increasing the potential application areas of stencil printing.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

The purpose of this paper is to present a detailed overview of the current stencil printing process for microelectronic packaging.

This paper gives a thorough review of stencil printing for electronic packaging including the current state of the art.

This article explains the different stencil technologies and printing materials. It then examines the various factors that determine the outcome of a successful printing process, including printing parameters, materials, apparatus and squeegees. Relevant technical innovations in the art of stencil printing for microelectronics packaging are examined as each part of the printing process is explained.

Stencil printing is currently the cheapest and highest throughput technique to create the mechanical and electrically conductive connections between substrates, bare die, packaged chips and discrete components. As a result, this process is used extensively in the electronic packaging industry and therefore such a review paper should be of interest to a large selection of the electronics interconnect and assembly community.

To investigate how jamming of particles in a solder paste varies as a function of the gap through which the particles flow, and to correlate this with skipping defects during the printing process.

Solder pastes with particle sizes of types 2, 3, 4 and 5 were sheared between the parallel plates of a rheometer. Jamming events that cause the solder particles to be forced against each other were detected by monitoring the electrical current flowing between the plates under a bias of 1.0 V or less. Solder paste printing trials were conducted with the same pastes, and solder paste skipping monitored.

Jamming was detected when the ratio of plate gap to largest particle diameter is reduced to a value between 3.8 and 5.0. Decreasing the gap further results in increased jamming. A strong correlation between levels of skipping and jamming was found.

More extensive printing trials are required before rheometric jamming detection can be used to predict printing performance.

The common rule of thumb used in solder paste printing that the aperture width should be no smaller than 4‐5 particle diameters is justified.

This paper presents a new technique for detecting jamming events which are too brief to be detected using normal rheometric techniques, but which have long been thought to be responsible for stochastic skipping defects during printing. Evidence supporting the link between jamming and this type of defect is presented.

This paper seeks to review recent advances in wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging.

Of the 91 journal papers, 59 were published in 2005‐2007 and topics related to wire bonding, flip chip and lead‐free solder for advanced microelectronics packaging are reviewed.

Research on advanced wire bonding is continuously performed for advanced and complex applications such as stacked‐dies wire bonding, wire bonding of low‐k ultra‐fine‐pitch devices, and copper wire bonding. Owing to its many advantages, flip chip using adhesive has gained more popularity. Research on the reliability of lead‐free solder joints is being conducted world‐wide. The new challenges, solutions and new developments are discussed in this paper.

Because of page limitation of this review paper and the large number of the journal papers available, only a brief review is conducted. Further reading is needed for more details.

This review paper attempts to provide introduction to recent developments and the trends in terms of the topics for advanced microelectronics packaging. With the references provided, readers may explore more deeply, focusing on a particular issue.

A measurement method has been developed to reveal the viscosity change of solder pastes during stencil printing. This paper aimed to investigate thixotropic behaviour, the viscosity change of a lead-free solder paste (Type 4).

The viscosity change of the solder paste during stencil printing cycles was characterised in such a way that the time-gap between the printing cycles was modelled with a rest period between every rheological measurement. This period was set as 15, 30 and 60 s during the research. The Cross model was fitted to the measurement results, and the η₀ parameter was used to characterise the viscosity change. The number of printing cycles necessary for reaching a stationary state in viscosity was determined for various rest periods.

It was found that the decrease in zero-shear viscosity is significant (25 per cent) in the first cycles, and it starts to become stationary at the sixth-seventh cycles. This means a printing process can provide the appropriate deposits only after the 7th cycle with the investigated Type 4 solder paste.

Time-dependent rheological behaviour of solder pastes was studied in the literature, but only the viscosity change over continuous time at constant shear rates was examined. The time-gap between stencil printing cycles was not considered, and thixotropic behaviour of solder pastes was also neglected. Therefore, the authors developed a measurement set which is able to model the effect of time-gap between printing cycles on the viscosity change of solder pastes.

The attack angle of stencil printing squeegees with different geometries was analysed using finite element modelling.

A finite element model (FEM) was developed to determine the attack angle during the stencil printing. The material properties of the squeegee were included in the model according to the parameters of steel AISI 4340, and the model was validated by experimental measurements. Two geometric parameters were investigated; two different unloaded angles (45° and 60°) and four overhang sizes of the squeegee (6, 15, 20 and 25 mm).

It was found that the deflection of the blade is nearly homogenous along the length of the squeegee. This implies that the attack angle does not change significantly along the squeegee length. The results showed significant differences between the initial and the attack angle. For example, the angle of the squeegee with 15 mm overhang size and with 60° initial angle decreased by more than 5° for a specific squeegee force of 0.3 N/mm; resulting in an attack angle of 53.4°.

The attack angle during the printing is considerably lower than the initial angle as a result of the printing force. The papers, which were dealing with the numerical modelling of the stencil printing presumed that the squeegees were having their initial angle. This could have led to invalid numerical results. Therefore, we decided to investigate the attack angle during stencil printing for squeegees with different initial geometries to enhance the numerical modelling of stencil printing.

Flip chip assembly using anisotropic conductive adhesives offers an interesting alternative for making high‐density interconnections. The use of conventional organic printed circuit boards makes this technique even more attractive. However, a low‐cost adhesive flip chip bonding process will require a reduced bonding cycle time or the use of multi‐head joining equipment. Adhesive flip chip bonding is characterized by a long bonding cycle time due to the relatively long curing time of adhesives and the need for simultaneous application of pressure during the curing process. In soldered flip chip techniques, the bonding time per assembly is shorter, because all the chips on the substrate can be soldered in a reflow oven at the same time. In this study, the minimum pre‐curing time needed to make a reliable adhesive joint was determined using one commercial anisotropic conductive adhesive film used on FR‐4 substrates. The results are promising, since bonding time reduction from 40 s to 10 s does not reduce the joint reliability.

In this study, flip‐chip (FC) assemblies on printed circuit board (PCB) and flex, with bump heights of 4, 20 and 40μm, and with a constant copper pad height were compared by modelling of the bonding process and of thermal cycling from –40 to 1258C. The stress distributions of the assemblies were analysed and it was found that the largest stresses occurred for the smallest bump height. The stresses in the anisotropic conductive film for the FC‐on‐flex assembly were also found to be generally larger than for the FC‐on‐PCB.