Search results

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five‐point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVE^TM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint remains constant. The technology is based on concepts that allow for the mass assembly and production of compliant packages both directly on the wafer and in “virtual wafer” format where individual chips are bonded directly to the flexible pellicle. This paper examines this important new packaging technology concept in terms of the process and device and the implications and future directions the technology is likely to take.

The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack.

This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point.

The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level.

There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).

In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.

It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.

In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

Known good die, flip chip and chip scale packages are technologies that offer various advantages to the board manufacturer. A discussion of the different types of package options, their methods of assembly, test and performance comparisons can help to resolve the general direction a manufacturer might pursue for next generation systems. This paper attempts to give a perspective as well as highlighting the areas of concern with the different options.

This study aims to investigate the options for additive rapid prototyping methods in microelectromechanical systems (MEMS) technology. Additive rapid prototyping technologies, such as stereolithography (SLA), fused deposition modeling (FDM) and selective laser sintering (SLS), all commonly known as three-dimensional (3D) printing methods, are reviewed and compared with the resolution requirements of the traditional MEMS fabrication methods.

In the 3D print approach, the entire assembly, parts and prototypes are built using various plastic and metal materials directly from the software file input, completely bypassing any additional processing steps. The review highlights their potential place in the overall process flow to reduce the complexity of traditional microfabrication and long processing cycles needed to test multiple prototypes before the final design is set.

Additive manufacturing (AM) is a promising manufacturing technique in micro-device technology.

In the current state of 3D printing, microfluidic and lab-on-a-chip devices for fluid handling and manipulation appear to be the most compatible with the 3D print methods, given their fairly coarse minimum feature size of 50-500 μm. Future directions in the 3D materials and method development are identified, such as adhesion and material compatibility studies of the 3D print materials, wafer-level printing and conductive materials development. One of the most important goals should be the drive toward finer resolution and layer thickness (1-10 μm) to stimulate the use of the 3D printing in a wider array of MEMS devices.

The review combines two discrete disciplines, microfabrication and AM, and shows how microfabrication and micro-device commercialization may benefit from employing methods developed by the AM community.