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As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost…
As a result of the trend towards portable communication products, low‐cost miniaturisation is becoming increasingly important. One of the methods to achieve low‐cost miniaturisation is flip‐chip assembly on FR4 boards. In this paper, two types of flip‐chip assembly process will be discussed: a process where flip‐chips with eutectic solder‐bumps are assembled by using a tacky flux, and a process where flip‐chips are assembled by using solder paste. Both processes have been verified on production boards, using production equipment. Demonstrated ppm defect levels are between 35 and 400 ppm (confidence level 95 per cent) at the solder joint level. Component yields for flip‐chips are between 99.2 and 100 per cent. The reliability of the assemblies fulfils consumer communication equipment requirements.
Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic…
Reports the research and development results on flip chip on FR‐4 and ceramics, using anisotropic conductive film (ACF), anisotropic conductive paste (ACP), or eutectic solder with underfill. Several types of ACF and ACP with different types of conductive particles and adhesives were investigated. Simple but high yield procedures for reworking flip chip on board using ACP and ACF were developed. Processes for flip chip on FR‐4 and ceramic boards using eutectic solder bumps with underfill were also evaluated. The flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the three processes (gold bumps with ACF, gold bumps with ACP, and eutectic solder bumps with underfill) is compared.
A flip chip on board technology fully compatible with current PCB facilities is reported. It used reflow soldering for chip attachment. It required electroless…
A flip chip on board technology fully compatible with current PCB facilities is reported. It used reflow soldering for chip attachment. It required electroless nickel/immersion gold finishing on the board pads as well as on the chip pads. A no‐clean solder paste was printed on the boards before chip placement. Thus, there was no requirement for solder deposition on the chip side. Assembly tests with various chip formats proved the feasibility of this technology. X‐ray inspection and cross‐sectioning revealed the good shape and alignment of the reflowed solder joints. The reliability of underfilled assemblies was studied by ‐40 to 125°C thermal cycling. This approach is especially suitable for prototype or low volume productions as it eliminates the solder bumping process on the chip side, which is usually performed on the wafer level.
Theelectronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip isgoing to become the major alternative for future products. The user wants…
The electronics packaging industry is debating whether CSP, Chip Scale Packaging, or flip chip is going to become the major alternative for future products. The user wants more functionality and portability at an ever increasing speed and the need for denser packaging is becoming urgent. The issue of acquiring adequate circuit boards is pressing. However, the comparison between CSP and flip chip is not straightforward, since many CSPs are really flip chips in small packages. CSPs therefore, do not compare with flip chip on board but with packaged die.
This paper discusses flip chip on FR‐4 and ceramics using non‐conductive adhesive (NCA), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). Several…
This paper discusses flip chip on FR‐4 and ceramics using non‐conductive adhesive (NCA), anisotropic conductive film (ACF), or anisotropic conductive paste (ACP). Several ACF and ACP materials with different types of adhesive resin and conductive particles and one NCA material were evaluated. Flip chips were assembled on test vehicles for temperature cycling and high‐temperature high‐humidity tests. The reliability performance of the processes was compared. Flip chip processes using NCA, ACF, or ACP could give satisfactory reliability and high assembly yield for some applications, when the bonding parameters were optimised.
Flip chip test boards with and without plasma enhanced chemical vapor deposition silicon nitride moisture barrier coatings were exposed to high humidity and temperature…
Flip chip test boards with and without plasma enhanced chemical vapor deposition silicon nitride moisture barrier coatings were exposed to high humidity and temperature cycling conditions. The effect of the stress developed in these environments was investigated and evaluated. The influence of the barrier layers on the extent of underfill delamination and degradation in flip chip assemblies was inspected by C‐mode Scanning Acoustic Microscopy. The moisture barrier layers studied show their potential to enhance the reliability of flip chip assemblies in humid environments.
The purpose of this paper is to assess the thermo-mechanical reliability of a solder bump with different underfills, with the evaluation of different underfill materials…
The purpose of this paper is to assess the thermo-mechanical reliability of a solder bump with different underfills, with the evaluation of different underfill materials. As there is more demand in higher input/output, smaller package size and lower cost, a flip chip mounted at the module level of a board is considered. However, bonding large chips (die) to organic module means a larger differential thermal expansion mismatch between the module and the chip. To reduce the thermal stresses and strains at solder joints, a polymer underfill is added to fill the cavity between the chip and the module. This procedure has typically, at least, resulted in an increase of the thermal fatigue life by a factor of ten, as compared to the non-underfilled case. Yet, this particular case is to deal with a flip chip mounted on both sides of a printed circuit board (PCB) module symmetrically (solder bump interconnection with Cu-Pillar). Note that Cu-Pillar bumping is known to possess good electrical properties and better electromigration performance. The drawback is that the Cu-Pillar bump can introduce high stress due to the higher stiffness of Cu compared to the solder material.
As a reliability assessment, thermal cyclic loading condition was considered in this case. Thermal life prediction was conducted by using finite element analysis (FEA) and modified Darveaux’s model, considering microsize of the solder bump. In addition, thermo-mechanical properties of four different underfill materials were characterized, such as Young’s modulus at various temperatures, coefficient of temperature expansion and glass transition temperature. By implementing these properties into FEA, life prediction was accurately achieved and verified with experimental results.
The modified life prediction method was successfully adopted for the case of Cu-Pillar bump interconnection in flip chip on the module package. Using this method, four different underfill materials were evaluated in terms of material property and affection to the fatigue life. Both predicted life and experimental results are obtained.
This study introduces the technique to accurately predict thermal fatigue life for such a small scale of solder interconnection in a newly designed flip chip package. In addition, a guideline of underfill material selection was established by understanding its affection to thermo-mechanical reliability of this particular flip chip package structure.
Most flip chip assemblies require underfill to bestow reliability that would otherwise be ravished by stress due to thermomechanical mismatch between die and substrate…
Most flip chip assemblies require underfill to bestow reliability that would otherwise be ravished by stress due to thermomechanical mismatch between die and substrate. While underfill can be viewed as “polymer magic” and the key to modern flip chip success, many see it as the process “bottleneck” that must be eliminated in the future. Both views are accurate. A substantial amount of R&D is being focused on making underfill more user‐friendly. Electronic materials suppliers, various consortia, government labs and university researchers are working diligently to shatter the bottleneck and fully enable flip chip ‐ the final destination for micropackaging. This paper will describe these efforts and provide a status report on state‐of‐the‐art underfill technologies. We will also examine new processing strategies.
Out‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can…
Out‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip‐chip on board (FCOB).
A 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values.
The present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature.
The 3D finite element approach considering the elasto‐plastic and temperature‐dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip‐chip assembly has been suggested.
This paper discusses chip removal and replacement processes of flip chip assemblies (FCAs) on printed wiring boards (PWBs). The original chip connection is achieved via mass reflow as in a surface mount assembly process. The FCA interconnection is one involving a surrogate solder bump on a chip and a lower melt solder on the PWB pads that fuses with the bump during reflow. The chip removal process thus entails melting the lower melt solder locally using hot gas. The following considerations will be discussed in the paper: chip size, chip removal methodology, local vs mass reflow for replacement attachment, solder height, the impact of multiple reflows on the solder joint integrity of assemblies. The use of the flip chip rework machine to remove ball grid arrays (BGAs) and quad flatpacks (QFPs) will be briefly addressed.