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The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V.

In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates.

The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP.

In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints.

The work has been carried out in two parts. In the first part, simulation results were generated using five different architectures; each designed using four logic design styles for three different transistor sizes. The designs were simulated to generate the values of worst‐case propagation delay and energy consumption per addition. This information is used for validating the delay and energy consumption per addition in the second part.

Optimum adder design under varying condition can be found out using this work.

The predictive model does not consider the variation in load capacitance of each cell.

At present, a prime requirement in application specific integrated circuit design is reduction in design cycle time. As a result, there is minimum scope for exploration of arithmetic units in order to choose the best‐suited design. This work will help the designers to choose an optimum adder design for a given set of requirements.

In this work, four degrees of freedom are taken in adder design space, which are not taken before. Here, the adder design space has been explored, studied, and analyzed in this study under so many varying conditions.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues.

The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design.

The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay.

The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.

Besides combinational circuits, sequential circuits, for instance, flip‐flops, also play an important role in the design of digital systems. In this article, energy‐recovery/adiabatic flip‐flops based on improved PAL‐2N logic with complementary pass transistor logic (CPL) evaluation tree (C‐PAL) family will be described. HSPICE simulation results show that the proposed SR and JK flip‐flops are able to achieve significant power savings compared to the conventional CMOS flip‐flops, with operating frequencies from 50MHz to 250MHz. The supply voltages are scaled down from 5V to 2.5V in order to compare the power consumption with CMOS counterpart. In addition, a 4‐bit binary counter is designed to verify the functionality of the proposed flip‐flops.

Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell.

Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles.

Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts.

The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

The purpose of chopper amplifier is to provide the wideband frequency to support biomedical signals.

This paper proposes a chopper-stabilized amplifier with a cascoded operational transconductance amplifier. The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor.

The total power consumption is 451 nW with a supplied voltage of 800 mV. The Gain and common mode rejection ratio are 48 dB and 78 dB, respectively.

All kinds of real time data analysis was not carried out, only few test samples related to EEG signals are validated because the real time chip was not manufactured due to funding issues.

The proposed work was validated with Monte-Carlo simulations. There is no external funding for the proposed work. So there is no fabrication for the design. But post simulations are performed.

The high impedance loop is established using an MOS pseudo resistor and with a tunable MOS capacitor. To the best of the author’s knowledge, this concept is completely novel and there are no publications on this work. All the modules designed for chopper amplifier are new concepts.

An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.