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Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor

Alok Kumar Mishra (Department of Electronics and Communication Engineering, National Institute of Technology Delhi, Delhi, India)
Vaithiyanathan D. (Department of Electronics and Communication Engineering, National Institute of Technology Delhi, Delhi, India)
Yogesh Pal (Department of Electronics and Communication Engineering, National Institute of Technology Delhi, Delhi, India)
Baljit Kaur (Department of Electronics and Communication Engineering, National Institute of Technology Delhi, Delhi, India)

Circuit World

ISSN: 0305-6120

Article publication date: 17 June 2021

Issue publication date: 16 June 2022

125

Abstract

Purpose

This work is proposed for low power energy-efficient applications like laptops, mobile phones, and palmtops. In this study, P-channel metal–oxide–semiconductor (PMOS)’s are used as access transistor in 7 transistors (7 T) Static Random Access Memory (SRAM) cell, and the theoretical Static Noise Margin (SNM) analysis for the proposed cell is also performed. A cell is designed using 7 T which consists of 4 PMOS and 3 NMOS. In this paper write and hold SNM is addressed and read SNM is also calculated for the proposed 7 T SRAM cell.

Design/methodology/approach

The authors have replaced N-channel metal–oxide–semiconductor (NMOS) access transistors with the PMOS access transistors, which results in proper data line recovery and provides the desired coupling. An error is likely to occur, if the read operation is performed too often probably by using the NMOS pass gate. It results in an improper recovery of the data line. Instead, by using PMOS as a pass gate, the time required for read operation can be brought down. As we know the mobility (µ) of the PMOS transistor is low, so the authors have used this property into the proposed design. When a low signal is applied to its control gate, the PMOS transistor come up with the desired coupling, when working as a pass gate.

Findings

Feedback switched transistor is used in the proposed circuit, which plays an important role in the write operation. This transistor is in OFF state and PMOS’s work as access transistor, when the proposed cell operating in read mode. This helps in the reduction of power. This work is simulated using UMC 40 nm technology node in the cadence virtuoso environment. The simulated result shows that, write power saving of 51.54% and 61.17%, hold power saving of 25.68% and 48.93% when compared with reported 7 T and 6 T, respectively.

Originality/value

The proposed 7 T SRAM cell provides proper data line recovery at a lower voltage when PMOS works as the access transistor. Power consumption is very less in this technique and it is best suitable for low power applications.

Keywords

Citation

Mishra, A.K., D., V., Pal, Y. and Kaur, B. (2022), "Design and mathematical analysis of a 7T SRAM cell with enhanced read SNM using PMOS as an access transistor", Circuit World, Vol. 48 No. 3, pp. 322-332. https://doi.org/10.1108/CW-05-2020-0095

Publisher

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Emerald Publishing Limited

Copyright © 2021, Emerald Publishing Limited

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