Search results

1 – 10 of 10
To view the access options for this content please click here
Article

Yavar Safaei Mehrabani, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi and Abolghasem Ghasempour

This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs).

Abstract

Purpose

This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs).

Design/methodology/approach

To design this cell, the capacitive threshold logic (CTL) has been used.

Findings

To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others.

Originality/value

This cell significantly reduces the number of transistors and only consists of NOT gates.

Details

Circuit World, vol. 45 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Hamidreza Uoosefian, Keivan Navi, Reza Faghih Mirzaee and Mahdi Hosseinzadeh

The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where…

Abstract

Purpose

The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors.

Design/methodology/approach

Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image.

Findings

Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder.

Originality/value

Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.

Details

Circuit World, vol. 46 no. 4
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Pramod Kumar Patel, M.M. Malik and Tarun Kumar Gutpa

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to…

Abstract

Purpose

The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells.

Design/methodology/approach

This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue.

Findings

The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart.

Research limitations/implications

Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit.

Practical implications

GNRFET devices are suitable for implementing low power and high density SRAM cell.

Social implications

The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices.

Originality/value

This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Details

Circuit World, vol. 46 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Robert Bogue

The purpose of this paper is to provide a review of recent developments in nanoelectronic devices, with an emphasis on the materials and fabrication technologies employed.

Abstract

Purpose

The purpose of this paper is to provide a review of recent developments in nanoelectronic devices, with an emphasis on the materials and fabrication technologies employed.

Design/methodology/approach

This paper focuses on three critical fields of nanoelectronics: integrated circuits (ICs), sensors and displays. It describes recent developments and considers the materials and techniques used in their fabrication.

Findings

This paper shows that nanoelectronic developments, particularly experimental ICs, are progressing very rapidly but all manner of different materials and non‐standard fabrication processes are involved. Major efforts are underway to develop simple and cost‐effective techniques which will allow the high volume production of suitable nanomaterials and their incorporation into commercial nanoelectronic devices.

Originality/value

The paper provides an up‐to‐date review of nanoelectronic device developments and fabrication technologies.

Details

Assembly Automation, vol. 30 no. 3
Type: Research Article
ISSN: 0144-5154

Keywords

To view the access options for this content please click here
Article

Afreen Khursheed and Kavita Khare

This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of…

Abstract

Purpose

This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.

Design/methodology/approach

Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.

Findings

An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.

Originality/value

Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

Details

Circuit World, vol. 46 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Md.Masud Rana, Dauda Sh. Ibrahim, M.R. Mohd Asyraf, S. Jarin and Amanullah Tomal

This review paper aims to focus on recent advances of carbon nanotubes (CNTs) to produce gas sensors. Gas sensors are widely used for monitoring hazardous gas leakages and…

Abstract

Purpose

This review paper aims to focus on recent advances of carbon nanotubes (CNTs) to produce gas sensors. Gas sensors are widely used for monitoring hazardous gas leakages and emissions in the industry, households and other areas. For better safety and a healthy environment, it is highly desirable to have gas sensors with higher accuracy and enhanced sensing features.

Design/methodology/approach

In this review, the authors focus on recent contributions of CNTs to the technology for developing different types of gas sensors. The design, fabrication process and sensing mechanism of each gas sensor are summarized, together with their advantages and disadvantages.

Findings

Nowadays, CNTs are well-known materials which have attracted a significant amount of attention owing to their excellent electrical, electronic and mechanical properties. On exposure to various gases, their properties allow the detection of gases using different methods. Therefore, over recent years, researchers have developed several different types of gas sensors along with other types of sensors for temperature, strain, pressure, etc.

Originality/value

The main purpose of this review is to introduce CNTs as candidates for future research in the field of gas sensing applications and to focus on current technical challenges associated with CNT-based gas sensors.

Details

Sensor Review, vol. 37 no. 2
Type: Research Article
ISSN: 0260-2288

Keywords

To view the access options for this content please click here
Article

Anil Kumar Uppugunduru and Syed Ershad Ahmed

Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules…

Abstract

Purpose

Multipliers that form the basic building blocks in most of the error-resilient media processing applications are computationally intensive and power-hungry modules. Therefore, improving the multiplier’s performance in terms of area, critical path delay and power has become an important research area. This paper aims to propose two improved multiplier designs based on a new approximate compressor circuit to reduce the hardware complexity at the partial product reduction stage. The proposed approximate 4:2 compressor design significantly reduces the overall hardware cost of the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure.

Design/methodology/approach

The multiplier designs implemented using the proposed approximate 4:2 compressor are targeted for error-resilient applications. For fair comparisons, various multiplier designs, including the proposed one, are implemented in MATLAB. The quality analysis is carried out using standard images, and metrics such as structural similarity index are computed to quantify the result of proposed designs with the existing architectures. Next, Verilog gate-level designs are synthesized to compute area, delay and power to prove the efficacy of the proposed designs.

Findings

Exhaustive error and hardware analysis have been carried out for the existing and proposed multiplier architectures. Error analysis carried out using MATLAB proves that the proposed designs achieve better quality metrics than existing designs. Hardware results show that area, the power consumed and critical path delay are reduced up to 39.8%, 51.7% and 15.9%, respectively, compared to the existing designs. Toward the end, the proposed designs impact is quantified and compared with existing designs on real-time image sharpening and image multiplication applications.

Originality/value

The area, delay and power metrics of the multiplier can be improved using an approximate compressor in an error-resilient application. Accordingly, in this work, a new compressor is proposed that reduces the hardware complexity in the multiplier architecture. However, the proposed approximate compressor, while reducing the computational complexity, tends to introduce error in the multiplier. The error introduced by the approximate compressor is reduced using a new technique of assigning inputs to the compressors in the partial product reduction structure. With the help of the approximate compressor and a technique of input realignment, hardware efficient and highly accurate multiplier designs are achieved.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Divya Madhuri Badugu, Sunithamani S., Javid Basha Shaik and Ramesh Kumar Vobulapuram

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

Abstract

Purpose

The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs).

Design/methodology/approach

To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset.

Findings

To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions.

Originality/value

The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

Details

Circuit World, vol. 47 no. 1
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Ali H. Majeed, Esam Alkaldy, Mohd Shamian Zainal, Keivan Navi and Danial Nor

Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique…

Abstract

Purpose

Quantum-dot cellular automata (QCA) has attracted computer scientists as new emerging nanotechnology for replacement the current CMOS technology because it has unique characteristics such as high frequency, extremely small feature size and low power consumption. The main building blocks in QCA are the majority gate and inverter so any Boolean function can be represented using these gates. Many important circuits were the target for implemented in this technology in an optimal form, such as random-access memory (RAM) cell. QCA-RAM cells were introduced in literature with different forms but most of them are not optimized enough. This paper aims to demonstrate QCA inherent capabilities that can facilitate the design of many important gates such as the XOR gate and multiplexer (MUX) without following any Boolean function to get an optimum design in terms of complexity and delay.

Design/methodology/approach

In this paper, a novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell. The proposed RAM cells are the lowest cost required compared with different counterparts. The presented RAM cells used a new approach that follows the new suggested block diagram. The presented circuits are simulated and tested with QCADesigner and QCAPro tools.

Findings

The comparison of the proposed circuits with the previously reported in the literature show noticeable improvements in speed, area, and the number of cells. The cost function analysis results for the proposed RAM cells show significant improvement compared to older circuits.

Originality/value

A novel structure of QCA-MUX in an optimal form will be used to design two unique structures of a RAM cell.

Details

Circuit World, vol. 46 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

To view the access options for this content please click here
Article

Hamidreza Ghanbari Khorram and Alireza Kokabi

Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are…

Abstract

Purpose

Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors.

Design/methodology/approach

This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency.

Findings

As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption.

Originality/value

Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

Details

Circuit World, vol. 46 no. 3
Type: Research Article
ISSN: 0305-6120

Keywords

1 – 10 of 10