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To evaluate the corrosion performance and nano‐mechanical behaviour of a brass substrate covered by different thick SiO₂ layers deposited by means of plasma enhanced chemical vapour deposition (PECVD) technique.

The comparison between laboratory and “industrial” objects revealed a very good corrosion behaviour and good mechanical performance of both of them: in particular it was possible to modulate the surface treatment to solve various problems from the industrial point of view.

It was possible to reduce the Cu migration into the SiO₂ coating during the PECVD deposition at a negligible level and to control it by the deposition; further, the nano‐indentation tests revealed the great utility of the coating annealing in obtaining a significant improvement of the mechanical properties of the coated objects.

Even if some industrial problems were solved (minimization of the presence of the coating defects and transparency of the coatings), some on the layer hardness (anti‐wear behaviour of the industrial objects) has to be better investigated and possibly solved.

The work reports a deposition process that is carried out industrially over a two year period.

This research reports a PECVD process realized on industrial objects: the originality is in the reached corrosion and mechanical performances that made it possible to realize a satisfactory industrial deposition.

The processing techniques and materials utilized in the fabrication of a two-terminal electrostatically actuated micro-electro-mechanical cantilever-arrayed device used for radio frequency tuning applications are presented in this work. The paper aims to discuss these issues.

The process, which is based on silicon surface micromachining, uses spin-coated photoresist as the sacrificial layer underneath the electroplated gold structural material and an insulating layer of silicon dioxide, deposited using plasma enhanced chemical vapour deposition (PECVD), to avoid a short circuit between the cantilever and the bottom electrode in a total of six major fabrication steps. These included the PECVD of the silicon dioxide insulating layer, optical lithography to transfer photomask layer patterns, vacuum evaporation to deposit thin films of titanium (Ti) and gold (Au), electroplating of Au, the dry release of the cantilever beam arrays, and finally the wafer dicing to split the different micro devices. These process steps were each sub-detailed to give a total of 14 micro-fabrication processes.

Scanning electron microscope images taken on the final fabricated device that was dry released using oxygen plasma ashing to avoid stiction showed 12 freely suspended micro-cantilevered beams suspended with an average electrostatic gap of 2.29±0.17 μm above a 4,934±3 Å thick silicon dioxide layer. Preliminary dimensional measurements on the fabricated devices revealed that the cantilevers were at least 52.06±1.93 μm wide with lengths varying from 377.97±0.01 to 1,491.89±0.01 μm and were at least 2.21±0.05 μm thick.

The cantilever beams used in this work were manufactured using electroplated gold, and photoresist was used as a sacrificial layer underneath the beams. Plasma ashing was used to release the beams. The beams were anchored to a central electrode and each beam was designed with varying length.

The purpose of this paper is to describe the fabrication of a miniaturized membrane type double cavity vacuum‐sealed micro sensor for absolute pressure using front‐side lateral etching technology.

Potassium hydroxide‐based anisotropic etching of single crystal silicon is used to realize the cavities under the membrane type diaphragms through channels on the sides. The diaphragms consist of composite layers of plasma‐enhanced chemical vapour deposition (PECVD) of silicon nitride and silicon dioxide. PECVD of silicon dioxide is done for sealing the channels and the cavity in vacuum. Boron thermal diffusion in low‐pressure chemical vapour deposition of polysilicon layer over the membrane is done for realizing resistors. The fabricated device uses Wheatstone half bridge circuit to read the variation of resistance with respect to an applied pressure.

A double cavity vacuum‐sealed absolute pressure micro sensor has been fabricated successfully using front‐side lateral etching technology and has been measured for pressure range of 0‐0.45 MPa. The measured pressure sensitivity of two pressure sensors is 9.28 and 10.44 mV/MPa.

The paper shows that front‐side lateral etching technology is feasible in the fabrication of small vacuum‐sealed cavities and absolute pressure sensors.

The purpose of this paper is to design a low-cost stress bimorph RF-MEMS switch which is the desired transmission area application.

The bimorph structure of the low-temperature plasma-enhanced chemical vapor deposition (PECVD) of thermal oxide and gold are utilized to create the vibrating membrane. The effects of process conditions of low-temperature oxide deposited using the PECVD technique enable stress-free deposition of the key structural layer.

Scanning electron microscope images of the RF micro-switch confirms negligible stress in the released structure. The RF performances of this device exhibit isolation around 43 dB of up to 50 GHz in the OFF-state position and an insertion loss of less than 0.18 dB in the ON-state.

The finite element method results show good isolation of 43 dB and less insertion loss of 0.18 dB.

In this paper, we aim to investigate the influence of the hydrogenated silicon nitride layers deposited by a large area 13.56 MHz plasma-enhanced chemical vapour deposition system on the electrical activity of the surface and interfaces of the grains for solar cells fabricated on microcrystalline silicon and multicrystalline silicon.

The characterization of current-voltage parameters of 25 cm² solar cells manufactured with different passivation and antireflective layers are presented. After spectral response measurements, external quantum efficiency was calculated, and the final results are shown graphically. The passivation effect concerning grain areas was evaluated more precisely by light-beam-induced current scan maps (LBIC).

The final impact of the type of passivation layer on surface and grain boundary photoconvertion in solar cells is determined.

The passivation effect concerning grain areas was evaluated more precisely by LBIC.

To fabricate submicrometer thin membrane of silicon nitride and silicon dioxide over an anisotropically etched cavity in (100) silicon.

PECVD of silicon dioxide and Silcion nitride layers of compatible thicknesses followed by thermal annealing in nitrogen ambients at 1,000°C for 30 min, leads to stable membrane formation. Anisotropic etching of (100) silicon below the membrane through channels on the sides has been used with controlled cavity dimensions.

Lateral front side etching through channels slows down etching rate drastically. The etching mechanism has been discussed with experimental details.

Vacuum sealed cavity membranes can be realised for micro sensor applications.

The process is new and feasible for micro sensor technologies.

Flip chip test boards with and without plasma enhanced chemical vapor deposition silicon nitride moisture barrier coatings were exposed to high humidity and temperature cycling conditions. The effect of the stress developed in these environments was investigated and evaluated. The influence of the barrier layers on the extent of underfill delamination and degradation in flip chip assemblies was inspected by C‐mode Scanning Acoustic Microscopy. The moisture barrier layers studied show their potential to enhance the reliability of flip chip assemblies in humid environments.

Three types of pattern on the monocrystalline silicon surface were prepared by using laser surface processing equipment. The DLC film and Si-DLC film on the patterning surface were deposited by using PECVD-2D plasma chemical vapor deposition sets. The paper aims to discuss these issues.

The tribological properties of the films were investigated by using the UMT-2 micro friction and wear tester. The surface topography, composition, hardness and elastic modular of the films were determined by Raman spectrum, nano mechanics tester and three-dimensional topography instrument. The worn surface topographies of the surface patterning films were tested by scanning electron microscopy.

The results show that the patterning monocrystalline silicon substrate surface has good anti-friction property under low load. The patterning DLC film and Si-DLC film surface have very good anti-friction property under all the test loads. The reason of these results is that the surface patterning film not only reduces the real contact area of the friction pairs but also has low surface bonding force.

This paper prepared three kinds of microscopic patterns on the monocrystalline silicon surface by using laser surface processing equipment. And then deposited DLC film and Si-DLC film on the patterning surface. All kinds of surface patterning monocrystalline silicon had very good anti-friction property under low load. And all kinds of surface patterning nano-hard film had perfect anti-friction property under all test loads.

A novel technology for a multichip module (MCM) on silicon is presented. The technology features the integration of a power and a ground plane, resulting in a five‐conductor layer module, the use of the heavily (n⁺) doped Si as the ground plane for integrated decoupling capacitances, integrated low TCR NiCr resistors, low resistance (13mΩ per square) TiW/Cu/TiW metallisation, high quality PECVD oxynitride (SiON) insulation layers, which are optimised to a low stress content, and a new wet‐dry etch technique for the vias. The module is able to handle 200MHz clock frequencies and, when carefully designed, can also be used for opto‐electronic interconnections in the GHz range. A test module for DC and HF characterisation has been designed and produced. Preliminary test results are presented.

The purpose of this study is to address the issue of technology equipment formerly dedicated to the process of 4- and even 5-inch photovoltaic cells and whose use has become critical with the evolution of silicon wafer size standards (M2–M10). Fortunately, the recent concept of 6'' half-cut cell with its many advantages appears promising insofar as it offers the possibility of further extend the use of costly, still operational process equipment, but doomed to obsolescence.

In the background of a detailed Al-BSF process, the authors show how to experimentally adapt specific accessories and arrange 6” half-wafers to enable the upgrade of a complete industrial process of silicon solar cells at a lower cost. Step by step, the implementation of the processes for the two wafer sizes (4” wafers and 6” half wafers) is compared and analyzed in terms of performance and throughput.

Globally, the same process effectiveness is observed for both types of wafers with slightly better sheet resistance uniformity for the thermal diffusion carried out on the half wafers; however, the horizontal arrangement of the wafer carriers in the diffusion and the plasma-enhanced chemical vapor deposition tubes limits the thermal balance regarding the total number of cells processed per batch.

In terms of the development of prototypes on a preindustrial scale, this paves the way to further continue operating outdated equipment for high-performance processes (passivated emitter and rear contact, Tunnel oxide passivated contact (TOPCon)), while complying with current standards for silicon wafers up to M10 format.