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A novel technology for a multichip module (MCM) on silicon is presented. The technology features the integration of a power and a ground plane, resulting in a five‐conductor layer module, the use of the heavily (n⁺) doped Si as the ground plane for integrated decoupling capacitances, integrated low TCR NiCr resistors, low resistance (13mΩ per square) TiW/Cu/TiW metallisation, high quality PECVD oxynitride (SiON) insulation layers, which are optimised to a low stress content, and a new wet‐dry etch technique for the vias. The module is able to handle 200MHz clock frequencies and, when carefully designed, can also be used for opto‐electronic interconnections in the GHz range. A test module for DC and HF characterisation has been designed and produced. Preliminary test results are presented.

The evolution of today's high speed electronic systems has resulted in the need for modules which are able to provide all chip‐to‐chip interconnection with very fine top level and buried conductor traces, and a dielectric with a very dense via grid pattern. As standard thick film technology is capable of pitches only down to 250 µm, new photoimageable thick film pastes have been developed in order to achieve a higher resolution. These materials allow one to combine the advantages of screen printing as a deposition technique with photolithography for the patterning. The image is produced by exposing the printed paste through a photomask to define either lines or vias, so that a very high resolution (50 (µm pitch), similar to that available in MCM‐D or MCM‐L, can be achieved. This paper describes the processing of the photoimageable dielectric and conductor pastes. As an example of the capability of this technology, a module for electro‐optical interconnection is presented.

The purpose of this paper is to investigate the behavior of embedded passives under changing temperature conditions. Influence of different temperature changes on the basic properties of embedded passives was analyzed. The main reason for these investigations was to determine functionality of passives for space application.

The investigations were based on the thin-film resistors made of Ni-P alloy, thick-film resistors made of carbon or carbon-silver inks, embedded capacitors made of FaradFlex materials and embedded inductor made in various configurations. Prepared samples were examined under the influence of a constant elevated temperature (100, 130 or 160°C) in a long period of time (minimum of 30 h), thermal cycles (from −40 to +85°C) or thermal shocks (from −40 to +105°C or from −40 to +125°C).

The achieved results revealed that resistance drift became bigger when the samples were treated at a higher constant temperature. At the same time, no significant difference in change in electrical properties for 50 and 100 Ω resistors was noticed. For all the tests, resistance change was below 2 per cent regardless of a value of the tested resistors. Conducted thermal shock studies indicate that thin-film resistors, coils and some thick-film resistors are characterized by minor variations in basic parameters. Some of the inks may show considerable resistance variations with temperature changes. Significant changes were also exhibited by embedded capacitors.

The knowledge about the behavior of the operating parameters of embedded components considering environmental conditions allow for development of more complex systems with integrated printed circuit boards.

Passive components integrated into a high‐density substrate can be a tolerable way to overcome the size and manufacturing limits of SMD passives mounted on to the system board. Still, this technology is perceived as being “too risky” and not cost‐effective. In this paper we propose a “passive optimized” solution combining the advantages from both SMD and integrated technology and avoiding the respective drawbacks. Exemplified by a GPS receiver front end, we present a methodology to assess the possible benefits when using the mixed technology.

To investigate the fabrication of integrated inductors on a liquid crystal polymer (LCP) substrate. To analyze the RF performance of the integrated inductors.

Fabrication of integrated inductors on a LCP substrate using an MCM‐D/L technique. A lumped element model of the integrated inductors is proposed. An analytical approach is used to extract the parameters in the model.

Integrated inductors on a LCP substrate have been fabricated using an MCM‐D/L technique. The conductor loss of the thin microstrip lines is the major factor degrading the Q‐value of the integrated inductors. A lumped element model of the integrated inductor is proposed. The parameters of the lumped element model can be extracted from the geometry of the integrated inductor. Further work will focus on increasing the conductor thickness from 500 nm to 5 μm.

The value of the paper lies in its description of the integration of inductors on a LCP substrate. It also describes how to extract parameters of the lumped element model of the integrated inductors from the geometry.

The opportunity for mutual benefit across Europe to develop low‐cost MCM technologies arose from recognition of the scientific skills and design and prototyping capabilities in organic and inorganic circuits in countries of Central Europe. As a result, the leading research institutions and small/medium‐size enterprises of Hungary, Romania and Slovenia together with relevant institutions of the UK and Belgium proposed and received approval for a European Union INCO‐Copernicus project “Cheap multichip models” to establish fast prototyping low cost multichip module (MCM) technology facilities. The project commenced in May 1997.