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Power electronics are usually soldered to Al₂‐O₃ direct‐bond‐copper (DBC) substrates to increase thermal diffusivity, while at the same time increasing electrical isolation. However, soldering gives rise to inherent residual stresses and out‐of‐plane deformation. The purpose of this paper is to look at the effect of soldering processes of Al₂‐O₃ DBC substrates to copper plates and power electronics, on their thermal fatigue life and warpage.

A numerical thermo‐mechanical finite element model, using the Chaboche material model, was developed to identify the thermal plastic strains evolved during soldering of DBC substrates to copper plates and power electronics. The plastic strains in conjunction with established extremely low cycle fatigue life prediction model for ductile material were used to predict the number of soldering cycles to failure. The predicted out‐of‐plane deformation and number of soldering cycles to failures was compared to realistic tests.

Soldering processes drastically reduce the thermal fatigue life of DBC substrates, giving rise to thermal cracking and premature failure. In this study the soldering process considered gave rise to out‐of‐plane deformations, consequently reducing heat dispersion in soldered DBC substrate assemblies. Furthermore, soldering gave rise to interface cracking and failed after three soldering cycles. Numerical finite element models were developed and are in good agreement with the experimental tests results.

The influence of soldering processes of DBC substrates to copper plates and electronics on the thermal fatigue life should be taken into consideration when establishing the design life of DBC substrates. Finite element models can be utilised to optimize soldering processes and optimize the design of DBC substrates.

The effect of soldering processes on DBC substrates was studied. A numerical finite element model used for the prediction of design life cycle and out‐of‐plane deformation is proposed.

Due to increasing density and high demands on electrical and thermal performance, modern packages require alternative chip interconnection and substrate technologies. Flip‐chip (FC) bonding is a suitable method for high interconnection densities. Compared with wire bonding and TAB, FC provides the highest contact density. This is due to the possibility of using the whole chip surface for bondpads (area bumps). In this paper, an adapted FC technology on green tape ceramic substrates was investigated. In order to reduce the substrate costs, FC bonding was performed directly on the thick film metallisation without the application of thin film technology for the upper substrate layers. Two solder bump metallurgies: PbSn95/5 and Au/Sn solder bumps were applied for fluxless FC bonding on adapted substrate metallisations. Fluxless soldering is performed by single chip bonding and requires substrates with narrow planarity tolerances. An alternative method using a wet eutectic Au/Sn solder paste on the substrate and Au bumps permits the application of substrates with standard planarity tolerances used in thick film applications. A common reflow of all chips of a multichip module is possible. First reliability results of metallurgical analysis and of the mechanical and electrical behaviour of the FC contacts after thermal cycling are presented.

Strain gauges can be realised by printing and firing thick‐film resistors on ceramic substrates that are usually based on alumina. However, sensing elements made on some other substrates – tetragonal zirconia or stainless steel – would exhibit some improved characteristics, either due to a lower modulus of elasticity or a higher mechanical strength. As thick‐film resistors are developed for firing on alumina substrates their compatibility and possible interactions with other kinds of substrates have to be evaluated. The sheet resistivities and noise indices of the resistors were comparable, whereas the gauge factors were lower for the dielectric‐on‐steel substrates. The temperature coefficients of resistivity (TCR) of the resistors on the ZrO₂ and dielectric‐on‐steel substrates were higher than the TCRs on the alumina substrates, which was attributed to the higher thermal expansion coefficient of the tetragonal zirconia and the stainless steel.

A novel interconnect technology, introducing thin film on a laminate substrate base, is presented. A specially constructed laminate board is used as a substrate for the thin film build‐up process. The main characteristics of the laminate core substrate are the z‐axis electrical connections, the absence of holes in the substrate and the very flat nature of the top surface. As a result, the base substrate can be processed further in a thin film processing line. The manufacturing and properties of these substrates are discussed.

A new hybrid substrate technology for power electronic applications has been characterised by thermal resistance and mechanical stress measurements. The new substrate utilises thermal spray technology for deposition of dielectric layer and electrical conductors. The results are compared with the more established technology of alumina substrates with direct copper bonding (DCB) metallisation. Silicon test chips for thermal resistance and mechanical stress measurement were used for the characterisation. The experimental results were compared with finite element analysis and a reasonable agreement was found.

The purpose of this paper is to address the influence of deposition process parameters. The substrate heating mechanisms are also discussed.

Deposition duration, sputtering power, working gas pressure, and substrate heater temperature on substrate heating in the direct current (DC) magnetron sputtering deposition process were investigated.

Results from the experiments show that, in DC magnetron sputtering deposition process, substrate heating is largely influenced by the process parameters and conditions.

This paper usefully demonstrates that substrate heating effects can be minimized by adjusting and selecting the proper sputtering process parameters; the production cost can be reduced by employing a higher sputtering power, lower working gas pressure and shorter deposition duration.

The electrodeposition of any metal over titanium substrates meets with many problems due to the formation of a non‐conductive layer of titanium oxide on the surface of substrates during the electroplating process. Trials were made to overcome these problems by the pre‐anodisation of titanium substrates in oxalic acid solution of concentration 100g/l, at high current density of 60‐95mA/cm^–2, and at ambient temperature. In these conditions, a thin, porous and conductive titanium oxide film can be obtained, which will then support electroplating processes. Rhodium metal was electrodeposited over the anodised titanium substrates from a bath consisting of Rh₂(SO₄)₃, 5.2g/l and H₂SO₄, 100g/l. At optimum conditions of electroplating, the rhodium electrodeposits were formed over the anodised titanium substrate with high adhesion, brightness and high current efficiency (92.05 per cent).

Printed flexible circuits that combined conventional silicon technology will enable the realisation of many value added products such as smart packaging for the fast moving consumer goods (FMCG) industry. This paper aims to describe an investigation into integrating silicon and printable circuits for the FMCG packaging industry and this would allow products with features such as brand protection, time temperature indicators, customer feedback and visual product enhancement. Responding to interest from the FMCG packaging industry, an investigation was carried out which investigated the printing conductive silver ink on common packaging substrates.

Standard IC mounting patterns were screen printed using two conductive silver materials (one high silver content traditional paste and one lower silver content gel polymer) to four plastic and three paper substrates which represent common FMCG substrates (HDPE, BOPP, PET and three paper substrates). Materials were characterised in terms of material rheology whereas prints were characterised through electrical performance and printed film topology.

There was a significant interaction between the substrate, silver ink formulation and the resultant line quality, line topology and conductivity. On paper substrates, the absorption of binder into the substrate resulted in denser silver packing and higher conductivity for the paste material. Higher conductivities were obtained on the substrates capable of withstanding higher curing temperatures. On the polymer substrates higher conductivity could be obtained by lower content silver materials due to the denser particle packing in the cured ink film as a result of its higher solvent/lower solids components.

Further work should examine the interactions for other printing processes commonly used in the FMCG industry such as rotogravure of flexography and should also examine nano particle materials. Further work should also address the mechanical adhesion of silicon logic on the substrates and bottlenecks in processing.

The lower silver content gel material potentially provides material cost reduction by a factor of between 4 and 7 for the same conductivity. The gel material also has potential for more uniform performance across all substrate types. Typically 3.1 Ω/cm resistance values are achieved on all substrates for 300 micron lines.

For those in the field of smart packaging the work has highlighted the interaction between silver materials and non PET/PEN substrates in flexible printed circuits. It has demonstrated the implications of rheology, substrate absorbency and materials processing temperature on circuit design. For those seeking printing process understanding it has provided further validation to support material transfer mechanisms in the screen printing process.

Direct‐bond‐copper (DBC) substrates crack after about 15 thermal cycles from −55 to 250°C. The purpose of this paper is to study the phenomenology of thermal‐cracking to determine the suitability of DBC for high‐temperature packaging.

The thermal plastic strain distribution at the edge of the DBC substrate was analyzed by using a finite element method with the Chaboche model for copper. The parameters of the Chaboche model were verified by comparing with the three‐point bending test results of DBC substrate. The thermal analyses involving different edge tail lengths indicated that susceptibility to cracking was influenced by the edge geometry of the DBC substrate.

Interface cracking was observed to initiate at the short edge of the bonded copper and propagated into the ceramic layer. The interface crack was caused by the accumulation of thermal plastic strain near the short edge. The edge tail can decrease the thermal strain along the short edge of the DBC substrate. Thermal cycling lifetime was improved greatly for the DBC substrate with 0.5 mm edge tail length compared with that without edge tail.

The thermal cracking of DBC substrates should be studied at the microstructure level in the future.

Thermal cycling induced failure of DBC was analyzed. A method of alleviating the thermal plastic strain distribution on the weakest site and improving the thermal fatigue lifetime of DBC substrates under thermal cycling was proposed.

This paper aims to study the influence of the Cu-Al₂O₃ film-coated Cu substrate as a thermal interface material (TIM) on the thermal and optical behaviour of the light-emitting diode (LED) package and the annealing effect on the thermal and optical properties of the films.

A layer-stacking technique has been used to deposit the Cu-Al₂O₃ films by means of magnetron sputtering, and the annealing process was conducted on the synthesized films.

In this paper, it was found that the un-annealed Cu-Al₂O₃–coated Cu substrate exhibited low value of thermal resistance compared to the bare Cu substrate and to the results of previous works. Also the annealing effect does not have a significant impact on the changes of properties of the films.

It is deduced that the increase of the Cu layer thickness can further improve the thermal properties of the deposited film, which can reduce the thermal resistance of the package in system-level analysis.

The paper suggested that the Cu-Al₂O₃–coated Cu substrate can be used as alternative TIM for the thermal management of the application of LEDs.

In this paper, the Cu substrate has been used as the substrate for the Cu-Al₂O₃ films, as the Cu substrate has higher thermal conductivity compared to the Al substrate as shown in previous work.