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Article
Publication date: 6 May 2020

Poornima Sridharan and Pugazhendhi Sugumaran C.

An annual substation equipment failure report says 3/7 capacitive voltage transformer (CVT) got damaged because of ferroresonance overvoltage. The conventional mitigation…

Abstract

Purpose

An annual substation equipment failure report says 3/7 capacitive voltage transformer (CVT) got damaged because of ferroresonance overvoltage. The conventional mitigation circuit fails to protect the transformer as the overvoltage may fall in the range between 2 and 4 per unit. It is necessary to develop a device to suppress the overvoltage as well as overcurrent of the CVT. This study aims to propose the suitability of memristor emulator as a mitigation circuit for ferroresonance.

Design/methodology/approach

The literature implies that a nonlinear circuit can protect the transformer against ferroresonance. An attempt is made with a memristor emulator using Operational Amplifier (OPAMP) for the mitigation of ferroresonance in a prototype transformer. The circuit is simulated using PSpice and validated for its ideal characteristics using hardware implementation. The nonlinear memductance is designed which is required to mitigate the ferroresonance. The mitigation performance has been compared with conventional method along with fast Fourier transform (FFT) analysis.

Findings

While the linear resistor recovers the secondary voltage by 74.1%, the memristor emulator does it by 82.05% during ferroresonance. Also, the total harmonic distortion (THD) of ferroresonance signal found to be 22.06% got improved as 2.56% using memristor emulator.

Research limitations/implications

The suitability of memristor emulator as a mitigation circuit for ferroresonance is proposed in this paper. As ferroresonance occurs in instrument transformers which have extra high voltage (EHV) rated primary windings and (110 V/[110 V/1.732]) rated secondary windings, the mitigation device is proposed to be connected as a nonlinear load across the secondary windings of the transformer. This paper discusses the preliminary work of ferroresonance mitigation in a prototype transformer. The mitigation circuit may have memristor or meminductor for ferroresonance mitigation when they are commercially available in future.

Practical implications

The electronic component-based memristor emulator may not work at 110 V practically as they may be rated at low power. Hence, chemical component-based memristor emulator was developed to do the same. The authors like to clarify that the memristor will be a solution for ferroresonance in future not the memristor emulator circuit.

Social implications

With the real form of memristor, the transistor world will be replaced by it and may have a revolution in the field of electronics, VLSI, etc. This contribution attempts to project the use of memristor in a smaller scale in high-voltage engineering.

Originality/value

The electronic component-based memristor emulator is proposed as a mitigation circuit for ferroresonance. The hypothesis has been verified successfully in a prototype transformer. Testing circuit of memristor emulator involves transformer, practically. The mitigation performance has been compared with conventional method technically and justified with FFT analysis.

Details

Circuit World, vol. 47 no. 1
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 20 July 2010

F.A. DiazDelaO and S. Adhikari

In the dynamical analysis of engineering systems, running a detailed high‐resolution finite element model can be expensive even for obtaining the dynamic response at few…

Abstract

Purpose

In the dynamical analysis of engineering systems, running a detailed high‐resolution finite element model can be expensive even for obtaining the dynamic response at few frequency points. To address this problem, this paper aims to investigate the possibility of representing the output of an expensive computer code as a Gaussian stochastic process.

Design/methodology/approach

The Gaussian process emulator method is discussed and then applied to both simulated and experimentally measured data from the frequency response of a cantilever plate excited by a harmonic force. The dynamic response over a frequency range is approximated using only a small number of response values, obtained both by running a finite element model at carefully selected frequency points and from experimental measurements. The results are then validated applying some adequacy diagnostics.

Findings

It is shown that the Gaussian process emulator method can be an effective predictive tool for medium and high‐frequency vibration problems, whenever the data are expensive to obtain, either from a computer‐intensive code or a resource‐consuming experiment.

Originality/value

Although Gaussian process emulators have been used in other disciplines, there is no knowledge of it having been implemented for structural dynamic analyses and it has good potential for this area of engineering.

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Article
Publication date: 5 March 2021

Kapil Bhardwaj and Mayank Srivastava

The purpose of the paper is to report an emulation configuration of a three pinch-off memristor (TPM), whose transient characteristics consist three cross-over points on…

Abstract

Purpose

The purpose of the paper is to report an emulation configuration of a three pinch-off memristor (TPM), whose transient characteristics consist three cross-over points on the voltage-current plane, which is dissimilar to a conventional memristor. These characteristics can be very useful in memristor-based multi-bit memory devices and hyperchaotic oscillators.

Design/methodology/approach

The work describes the Mathematical framework for TPM and a circuit emulator based on the derived conditions. The configuration is based on five operational transconductance amplifier (OTAs) and four grounded passive elements. After which, we have verified its operation using personal simulation program with integrated circuit emphasis simulation environment. Finally, the implementation of OTA-based TPM using commercial integrated circuit (IC) LM13700 has also been presented.

Findings

It has been shown that a flux-dependent memductance expression of cubic order can show three intersections on the VI contour under certain parameter related constraints. Moreover, the OTA-based emulator reported in the work is very compact in nature because of the no use of external multiplier IC/circuitry, which has been popular in previous emulators.

Originality/value

For the first time, a multiple cross-over memristor emulator has been reported which can operate under practical operating conditions such as at practical operating frequencies and sinusoidal excitation.

Details

Circuit World, vol. ahead-of-print no. ahead-of-print
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 31 December 2020

Kapil Bhardwaj and Mayank Srivastava

This paper aims to develop a mathematical model for four-lobe memristor (FLM) element. The four-lobe memristive behaviour can be used in realization of hyperchaotic…

Abstract

Purpose

This paper aims to develop a mathematical model for four-lobe memristor (FLM) element. The four-lobe memristive behaviour can be used in realization of hyperchaotic oscillators and implementation of multi-bit memories. For verification of the developed mathematical framework, two FLM circuit emulators have been presented using VDCC and IC LM13700, respectively.

Design/methodology/approach

A mathematical model for FLM has been developed in which, the condition for the existence of symmetrical four lobes, instances and coordinates of the end points of lobes has been derived and presented. Using this mathematical framework, a FLM emulator based on VDCC has been developed. To validate the possibility of practical implementation of FLM concept, an IC LM13700-based circuit has also been developed. The workability of VDCC based circuit has been verified by running simulations in PSPICE environment using CMOS VDCC model. Similarly, the behaviour of LM13700 IC-based circuit has been confirmed by SPICE model of LM13700 IC.

Findings

It has been shown mathematically that under certain conditions, third-order flux dependent equation of memductance can be used to generate four lobes on the transient v-i plane. Also, two FLM emulators without using any voltage multiplier circuit/IC have been reported.

Originality/value

From the best knowledge of the authors, there are no such FLM emulators that have been reported in literature so far, which operates at practical operating frequencies.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering , vol. 40 no. 1
Type: Research Article
ISSN: 0332-1649

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Article
Publication date: 4 October 2018

Bocheng Bao, Jiaoyan Luo, Han Bao, Quan Xu, Yihua Hu and Mo Chen

The purpose of this paper is to construct a proportion-integral-type (PI-type) memristor, which is different from that of the previous memristor emulator, but the…

Abstract

Purpose

The purpose of this paper is to construct a proportion-integral-type (PI-type) memristor, which is different from that of the previous memristor emulator, but the constructing memristive chaotic circuit possesses line equilibrium, leading to the emergence of the initial conditions-related dynamical behaviors.

Design/methodology/approach

This paper presents a PI-type memristor emulator-based canonical Chua’s chaotic circuit. With the established mathematical model, the stability region for the line equilibrium is derived, which mainly consists of stable and unstable regions, leading to the emergence of bi-stability because of the appearance of a memristor. Initial conditions-related dynamical behaviors are investigated by some numerically simulated methods, such as phase plane orbit, bifurcation diagram, Lyapunov exponent spectrum, basin of the attraction and 0-1 test. Additionally, PSIM circuit simulations are executed and the seized results validate complex dynamical behaviors in the proposed memristive circuit.

Findings

The system exhibits the bi-stability phenomenon and demonstrates complex initial conditions-related bifurcation behaviors with the variation of system parameters, which leads to the occurrence of the hyperchaos, chaos, quasi-periodic and period behaviors in the proposed circuit.

Originality/value

These memristor emulators are simple and easy to physically fabricate, which have been increasingly used for experimentally demonstrating some interesting and striking dynamical behaviors in the memristor-based circuits and systems.

Details

Circuit World, vol. 44 no. 4
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 26 August 2014

Michael Roland, Josef Langer and Rene Mayrhofer

The purpose of this paper is to address the design, implementation, performance and limitations of an environment that emulates a secure element for rapid prototyping and…

Abstract

Purpose

The purpose of this paper is to address the design, implementation, performance and limitations of an environment that emulates a secure element for rapid prototyping and debugging. Today, it is difficult for developers to get access to a near field communication (NFC)-secure element in current smartphones. Moreover, the security constraints of smartcards make in-circuit emulation and debugging of applications impractical. Therefore, an environment that emulates a secure element brings significant advantages for developers.

Design/methodology/approach

The authors' approach to such an environment is the emulation of Java Card applets on top of non-Java Card virtual machines (e.g. Android Dalvik VM), as this would facilitate the use of existing debugging tools. As the operation principle of the Java Card VM is based on persistent memory technology, the VM and applications running on top of it have a significantly different life cycle compared to other Java VMs. The authors evaluate these differences and their impact on Java VM-based Java Card emulation. They compare possible strategies to overcome the problems caused by these differences, propose a possible solution and create a prototypical implementation to verify the practical feasibility of such an emulation environment.

Findings

While the authors found that the Java Card inbuilt persistent memory management is not available on other Java VMs, they present a strategy to model this persistence mechanism on other VMs to build a complete Java Card run-time environment on top of a non-Java Card VM. Their analysis of the performance degradation in a prototypical implementation caused by additional effort put into maintaining persistent application state revealed that the implementation of such an emulation environment is practically feasible.

Originality/value

This paper addresses the problem of emulating a complete Java Card run-time environment on top of non-Java Card virtual machines which could open and significantly ease the development of NFC secure element applications.

Details

International Journal of Pervasive Computing and Communications, vol. 10 no. 3
Type: Research Article
ISSN: 1742-7371

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Article
Publication date: 28 January 2020

Huijun Gan, Dongsheng Yu, Dongkun Li and He Cheng

The purpose of this paper is to construct a flux-controlled memcapacitor (MC) emulator without grounded restriction with the binary operation ability. The active…

Abstract

Purpose

The purpose of this paper is to construct a flux-controlled memcapacitor (MC) emulator without grounded restriction with the binary operation ability. The active first-order low-pass filter (LPF) and high-pass filter (HPF) circuits are constructed by replacing the capacitor with MC.

Design/methodology/approach

The output saturation of the active device is innovatively adopted to realize the binary operation of MC with two memcapacitance values. By applying the direct current control voltage together with the input signal, the memcapacitance can be controlled, and hence, cut-off frequency of the filters can be adjusted without changing the circuit structure.

Findings

Experiments and simulation results show that the new filter has good frequency selectivity. Both LPF and HPF can change the cut-off frequency by changing the positive and negative control voltage. The experimental and simulation results are in good agreement with the theoretical analysis, which proves the feasibility and validity of the emulator and the filters.

Originality/value

These MC emulators are simple and easy to physically fabricate, which have been increasingly used for experiment. It also provide an effective reference for device miniaturization and low power consumption.

Details

Circuit World, vol. 46 no. 2
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 7 November 2016

Shao-Fu Wang and D.Z. Xu

This paper aims to propose the modeling of nanostructured memristor, and the circuit of amplitude modulator was designed and analyzed with memristor. The simulation…

Abstract

Purpose

This paper aims to propose the modeling of nanostructured memristor, and the circuit of amplitude modulator was designed and analyzed with memristor. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

Design/methodology/approach

The modeling of nanostructured memristor is proposed in this paper, and the circuit of amplitude modulator was designed and analyzed with memristor, amplifiers and BPF device. For measuring the modulated signal, the emulator circuit of memristor is designed. The simulation results show that the nanostructured memristor can be utilized to implement the desired amplitude modulated signal.

Findings

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given.

Originality/value

The innovations of this work are as follows: the AM modulator circuit using memristor has been proposed, analyzed and simulated. The emulator of memristor is given, and the results of this work demonstrate that the nonlinearity of the memristor can be used to generate the desired amplitude modulation free of harmonic sidebands, because of distortion of the modulating signal.

Details

Circuit World, vol. 42 no. 4
Type: Research Article
ISSN: 0305-6120

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Article
Publication date: 7 June 2013

Yuri Takhteyev and Quinn DuPont

The paper's aim is to describe the world of retrocomputing, a constellation of largely non‐professional practices involving old computing technology. It seeks to show how…

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Abstract

Purpose

The paper's aim is to describe the world of retrocomputing, a constellation of largely non‐professional practices involving old computing technology. It seeks to show how retrocomputing serves the goals of collection and preservation, particularly in regards to historic software, and how retrocomputing practices challenge traditional notions of authenticity. It then seeks to propose an alternative conceptualization and suggest new avenues for collaboration between retrocomputing practitioners and memory institutions.

Design/methodology/approach

The paper is based on extensive observation of retrocomputing projects, conducted primarily online.

Findings

Retrocomputing includes many activities that can be seen as constituting collection and preservation. At the same time, it is often transformative, producing assemblages that “remix” fragments from the past with newer elements or joining together historic components that were never combined before. While such “remix” may seem to undermine preservation, it also allows for fragments of computing history to be reintegrated into a living, ongoing practice, contributing to preservation in a broader sense. The seemingly unorganized nature of retrocomputing assemblages also provides space for alternative “situated knowledges” and histories of computing, which can sometimes be quite sophisticated.

Research limitations/implications

Retrocomputing challenges established notions of collection and preservation. A “situated knowledges” perspective provides a possible resolution.

Practical implications

Retrocomputing presents memory institutions (and libraries in particular) with an opportunity for new forms of collaboration in collection and preservation of software applications.

Originality/value

The paper puts at the center the ways in which retrocomputing challenges the established notions of collection and preservation. It offers alternative conceptualizations that suggest new forms of collaboration.

Details

Library Hi Tech, vol. 31 no. 2
Type: Research Article
ISSN: 0737-8831

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Article
Publication date: 1 March 2013

A.W. Ruan, C.Q. Li, Z.J. Song and W.C. Li

Increasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation…

Abstract

Purpose

Increasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.

Design/methodology/approach

The debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.

Findings

This method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.

Originality/value

The proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

Details

COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, vol. 32 no. 2
Type: Research Article
ISSN: 0332-1649

Keywords

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