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To model the differential dc gain, base resistance, and current voltage performance of 4H‐Silicon Carbide (SiC) bipolar junction transistors (BJT) operating at and above room temperature. Accurate modeling will result in improved process efficiency, interpretation of experimental data, and insight into device behavior.

The PISCES two dimensional device simulation program is used to allow for modeling the behavior of 4H‐SiC BJT. The physical material parameters in PISCES such as carrier's mobility and lifetime, temperature dependent bandgap, and the density of states are modified to accurately represent 4H‐SiC. The simulation results are compared with the measured experimental data obtained by others. The comparisons made with the experimental data are for two different devices that are of interest in power electronics and RF applications.

The simulation results predict a dc current gain of about 25 for power device and a gain of about 20 for RF device in agreement with the experimental data. The comparisons confirm the accuracy of the modeling employed.

The simulated current‐voltage characteristics indicate that higher gain may be achieved for 4H‐SiC transistors if the leakage current is reduced.

The simulation work discussed in this paper complements the current research in the design and characterization of 4H‐SiC bipolar transistors. The model presented will aid in interpreting experimental data at a wide range of temperatures.

This paper reports on a new model that provides insight into the device behavior and shows the trend in the dc gain performance important for the design and optimization of 4H‐SiC bipolar transistors operating at or above the room temperature.

The purpose of this paper is to develop a method for multiple soft fault diagnosis of nonlinear circuits including fault detection, identification of faulty elements and estimation of their values in real circumstances.

The method for fault diagnosis proposed here uses a measurement test leading to a system of nonlinear equations expressing the measured quantities in terms of the circuit parameters. Nonlinear functions, which appear in these equations are not given in explicit analytical form. The equations are solved using a homotopy concept. A key problem of the solvability of the equations is considered locally while tracing the solution path. Actual faults are selected on the basis of the observation that the probability of faults in fewer number of elements is greater than in a larger number of elements.

The results indicate that the method is an effective tool for testing nonlinear circuits including bipolar junction transistors and junction field effect transistors.

The homotopy method is generalized and associated with a restart procedure and a numerical algorithm for solving differential equations. Testable sets of elements are found using the singular value decomposition. The procedure for selecting faulty elements, based on the minimal fault number rule, is developed. The method comprises both theoretical and practical aspects of fault diagnosis.

The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition.

The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation.

We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime.

The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

The transient simulation of integrated circuit has become very expensive in terms of computer time due to increase in the number of transistors in typical simulation. Spectral technique and Chebyshev polynomials offers an efficient alternative algorithm for simulation of integrated circuits. In this paper an automatic formulation of circuit elements and transistor models, built in MOS technology, for analysis using spectral technique is presented. The algorithm is implemented and the simulation is proven to require less computer time than in the case of SPICE or ASTAP

This paper presents a computer‐aided design (CAD) tool for the design of isolated dc‐dc converters.

This tool, developed in Matlab environment, is based on multiobjective optimization (MO) using genetic algorithms. The Elitist Nondominated Sorting Genetic Algorithm is used to perform search and optimization whereas analytical models are used to model the power converters. The design problem requires minimizing the weight, losses and cost of the converter while ensuring the satisfaction of a number of constraints. The optimization variables are, as for them, the operating frequency, the current density, the maximum flux density, the transformer dimensions, the wire diameter, the core material, the conductor material, the converter topology (among Flyback, Forward, Push‐Pull, half‐bridge and full‐bridge topologies), the number of semiconductor devices associated in parallel, the number of cells associated in series or parallel as well as the kinds of input and output connections (serial or parallel) of these cells. Finally, the design of an auxiliary railway power supply is presented and discussed.

The results show that such tool to design dc‐dc power converters presents several advantages. In particular, it proposes to the designer a set of solutions – instead of a single one – so that he can choose a posteriori which solution best fits the application under consideration. Moreover, interesting solutions not considered a priori can be found with this tool.

To the best of the authors’ knowledge, such a CAD tool including a MO procedure taking several topologies into account has not been suggested so far.

This study aims to propose a methodology by integrating three approaches, namely, internal core technology, external knowledge flow and industrial technology development to help companies improve their decision-making quality for technology planning and enhance their research and development (R&D) portfolio efficiency.

The primary focus of this study is thin-film solar technology and patent data is retrieved from the United States Patent and Trademark Office (USPTO) database. This study presents a methodology based on the proposed integrated analysis method, constructed with patent indicators, centrality analysis of social networks and main path analysis.

The results of this study can be itemized as – the core technological competency: companies involved in two specific technology fields have lower strength in R&D portfolio than leading companies with single-core technology. Knowledge flow: most companies in a network are knowledge producers/absorbers and technological development: diverse source and sink nodes were identified in the global main path during 1997-2003, 2004-2010 and 2011-2017.

Latecomer companies can emulate leaders’ innovation and enhance their technological competence to seek niche technology. Using the global main path, companies monitor outdated technologies that can be replaced by new technologies and aid to plan R&D strategy and implement appropriate strategic decisions avoiding path dependency.

The knowledge accumulation process helps in identifying the change of position and the role of companies; understanding the trend of industrial technology knowledge helps companies to develop new technology and direct strategic decisions. The novelty of this research lies in the integrated approach of three methods aiding industries to find their internal core technical competencies and identify the external position in the competitive market.

The aim of this paper is to find the electrical representation of a solid oxide fuel cell (SOFC) that enables the application of typical exploitation characteristics of fuel cells for estimation of fuel cell parameters (for example, exchange current) and easy analysis of phenomena occurred during the fuel cell operation.

Three-layer structure of an SOFC, where a thin semi-conducting layer of electrolyte separates the anode from the cathode, shows a strong similarity to typical semiconductor devices built on the basis of P-N junctions, like diodes or transistors. Current–voltage (I-V) characteristics of a fuel cell can be described by the same mathematical functions as I-V plots of semiconductor devices. On the basis of this similarity and analysis of impedance spectra of a real fuel cell, two electrical representations of the SOFC have been created.

The simplified electrical representation of SOFC consists of a voltage source connected in series with a diode, which symbolizes a voltage drop on a cell cathode, and two resistors. This model is based on the similarity of Butler-Volmer to Shockley equation. The advanced representation comprises a voltage source connected in series with a bipolar transistor in close to saturation mode and two resistors. The base-emitter junction of the transistor represents voltage drop on the cell cathode, and the base-collector junction represents voltage drop on the cell anode. This model is based on the similarity of Butler-Volmer equation to Ebers-Moll equation.

The proposed approach based on the Shockley and Ebers-Moll formulas enables the more accurate estimation of the ion exchange current and other fuel cell parameters than the approach based on the Butler-Volmer and Tafel formulas. The usability of semiconductor models for analysis of SOFC operation was proved. The models were successively applied in a new design of a planar ceramic fuel cell, which features by reduced thermal capacity, short start-up time and limited number of metal components and which has become the basis for the SOFC stack design.

SINCE the early years of the last decade a great deal of research has been done on the properties of the new class of materials called semiconductors because their electrical properties lie between those of conductors and insulators. Some of the results of these researches are described in this article, in particular those which are of interest to aircraft engineers. A simple explanation of the mechanism of these devices is given and some emphasis is laid on work done by staff and students of the Department of Aircraft Electrical Engineering at The College of Aeronautics.

A compound emitter heterojunction bipolar transistor (HBT) structure that incorporates an additional heterojunction within the emitter for minority carrier confinement has been proposed. In this new device configuration, the single wide band‐gap emitter layer in a conventional HBT is replaced by two sub‐layers of wide band‐gap material, with the sub‐layer nearer the base having a narrower band‐gap. By means of numerical simulations, the compound emitter HBT was found to perform better than comparable conventional HBTs. With the AlGaAs(n) / GaAs heterostructure system, the optimum compound emitter HBT structure was found to be Al0.3Ga0.7As(n) ‐ Al0. 2Ga0.8As(n) / GaAs with grading at the two hetero‐interfaces. It has a low turn‐on voltage that is almost identical to that of a homojunction GaAs bipolar transistor with similar doping conditions. Compared with a conventional single emitter layer Al0.3Ga0.7As/GaAs HBT, the optimum compound emitter HBT has an enhancement in the current gain by approximately 2 folds, an improvement in the uniform current gain region from 2 to 4 decades of collector current density, and a slight increase in the unity‐gain cut‐off frequency fT by about 7 %.

The purpose of this paper is to compare different junctions' parameters extraction models.

I‐V curves of p⁺‐n and p_well‐n diodes were measured. Five models for parameters extraction on I‐V characteristics of diodes in an educational poly‐Si gate p_well complementary metal oxide semiconductor (CMOS) technology were applied. The junctions' areas were 30 × 30 μm for the source‐body p⁺‐n junction of the PMOS transistor and 220 × 250 μm for the p_well‐body junction. The diodes were sintered in forming gas (10 percent of H₂) in the temperature interval of 450‐525°C for times from 30 min up to 4 h.

It was shown that the best annealing regimes are different for both kinds of junctions.

The paper shows that the best annealing regime for p⁺‐n diodes (the lowest n and I₀ values) is 450°C, 30 min and for the p_well‐n diodes (the lowest I₀ values) is 525°C, 60 min. So, for the different kinds of junctions in one integrated circuit, different annealings could give the best parameters and the optimization depends on the specific characteristics of the developed technology.