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Owing to the high cost of data acquisition (DAQ) card in the market, the purpose of this paper is to develop a high speed, low‐cost microprocessor and ethernet controller‐based DAQ in optical tomography system.

Microprocessor is the main core to control the sensor circuitry while ethernet controller has the responsibility of transmitting data to PC and thus insuring the reliability of data.

The data transfer rate will be up to megabytes per seconds. In this optical tomography system, projection geometry combining two orthogonal and two rectilinear in one layer is modeled.

This paper presents a new application in optical tomography.

In real-time entertainment processing applications, processing of the multiple data streams demands high efficient multiple transfers, which leads to the computational overhead for system-on-chip (SoC), which runs the artificial intelligence algorithms. High-performance direct memory access controller (DMAC) is incorporated in SoC to perform the multiple data transfers without the participation of main processors. But achieving the area-efficient and power-aware DMAC suitable for streaming the multiple data remains to be a daunting challenge among the researchers.

The purpose of this paper to provide the DMA operations without intervention of central processing unit (CPU) for bulk video data transmissions.

The proposed DMAC has been developed based on the hybrid advanced extensible interface (AXI)-PCI bus subsystem to handle the multiple data streams from the video sources. The proposed model consists of bus selector module, user control signal, status register, DMA-supported address and AXI-PCI subsystems to achieve better performance in analysing the video frames.

The extensive experimentation is carried out with Xilinx Zynq SoC architecture using Very High Speed integrated circuit hardware description language (VHDL) programming, and performance metrics such as utilization area and power are calculated and compared with the other existing DMA controllers such as Scatter-DMA, Gather-DMA and Enhanced DMA. Simulation results demonstrate that the proposed DMAC has outperformed other existing DMAC in terms of less area, less delay and power, which makes the proposed model suitable for streaming multiple video streams.

Deep learning techniques are unavoidable in a variety of domains such as health care, computer vision, cyber-security and so on. These algorithms demand high data transfers but require bottlenecks in achieving the high speed and low latency synchronization while being implemented in the real hardware architectures. Though direct memory access controller (DMAC) has gained a brighter light of research for achieving bulk data transfers, existing direct memory access (DMA) systems continue to face the challenges of achieving high-speed communication. The purpose of this study is to develop an adaptive-configured DMA architecture for bulk data transfer with high throughput and less time-delayed computation.

The proposed methodology consists of a heterogeneous computing system integrated with specialized hardware and software. For the hardware, the authors propose an field programmable gate array (FPGA)-based DMAC, which transfers the data to the graphics processing unit (GPU) using PCI-Express. The workload characterization technique is designed using Python software and is implementable for the advanced risk machine Cortex architecture with a suitable communication interface. This module offloads the input streams of data to the FPGA and initiates the FPGA for the control flow of data to the GPU that can achieve efficient processing.

This paper presents an evaluation of a configurable workload-based DMA controller for collecting the data from the input devices and concurrently applying it to the GPU architecture, bypassing the hardware and software extraneous copies and bottlenecks via PCI Express. It also investigates the usage of adaptive DMA memory buffer allocation and workload characterization techniques. The proposed DMA architecture is compared with the other existing DMA architectures in which the performance of the proposed DMAC outperforms traditional DMA by achieving 96% throughput and 50% less latency synchronization.

The proposed gated recurrent unit has produced 95.6% accuracy in characterization of the workloads into heavy, medium and normal. The proposed model has outperformed the other algorithms and proves its strength for workload characterization.

Vision sensor for arc weld seam tracking uses a projected line of light scan from a high power infrared LED, which is detected by a two‐dimensional position‐sensitive photocell. It is compact enough to be mounted on a robot hand and works well on surfaces of poor reflectivity.

Cracked screw heads have, as this paper describes, been automatically detected by a solid state electronic linescanning camera. The equipment which includes an automatic feeding system and fibre optic component illumination is controlled by a microprocessor.

Druck has introduced the aeronautical version of its recently announced DPI 145 digital pressure indicator, which is said to be capable of meeting test and measurement requirements in meteorology, aerospace, and on the airfield.

INCAA is a computer systems house whose primary objectives are the development, manufacture and support of special systems for industry and science. Applying modern technology, INCAA has developed in addition to the CAMAC range of microprocessor modules, a modular system based on the Eurocard standard printed circuit boards and connectors.

The attempt to establish a common European framework for core platforms' duties and responsibilities toward other actors in the digital environment is at the core of the recent scholarly debate surrounding the Digital Markets Act (DMA) proposal. In particular, the everlasting juxtaposition between the “data power” – as emerging from recent cases (Section 2) – that dominant tech companies enjoy and the concept of consumer sovereignty (Section 3) lies at the core of the proposal's attempt to identify digital core platforms as market gatekeepers. Accordingly, this chapter critically investigates the divide between power imbalance and consumer sovereignty in light of the architecture designed by the DMA, with a specific focus on its effectiveness in identifying gatekeepers' power drivers (Section 4). After highlighting the main critical aspects of the pertinent rules, opportunities for fruitful developments are then identified through the reframing of some of the notions considered in the proposal, and namely the role of “lock-in” effects and “data accumulation” (Section 5). Lastly, this chapter suggests that the DMA advancements – while desirable – are bound to be fragmentary in the absence of a wider appraisal of the nature of data power imbalance dynamics in the modern digital markets (Section 6).