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The purpose of this paper is to develop an field programmable gate array (FPGA)-based neuron circuit to mimic dynamical behaviors of tabu learning neuron model.

Numerical investigations for the tabu learning neuron model show the coexisting behaviors of bi-stability. To reproduce the numerical results by hardware experiments, a digitally FPGA-based neuron circuit is constructed by pure floating-point operations to guarantee high computational accuracy. Based on the common floating-point operators provided by Xilinx Vivado software, the specific functions used in the neuron model are designed in hardware description language programs. Thus, by using the fourth-order Runge-Kutta algorithm and loading the specific functions orderly, the tabu learning neuron model is implemented on the Xilinx FPGA board.

With the variation of the activation gradient, the initial-related coexisting attractors with bi-stability are found in the tabu learning neuron model, which are experimentally demonstrated by a digitally FPGA-based neuron circuit.

Without any piecewise linear approximations, a digitally FPGA-based neuron circuit is implemented using pure floating-point operations, from which the initial conditions-related coexisting behaviors are experimentally demonstrated in the tabu learning neuron model.

Flying‐capacitor multilevel converters (FCC) need a passive or active regulation of the capacitor voltages. Recently the trend is towards active control, often implemented separately from the current control. The advantages of a true multi‐variable control sparked the interest to apply Model Based Predictive Control (MBPC) for FCC. In this paper an objective analysis method to evaluate the effects of several design choices is presented. The effects of the weight factor selection, model simplification, and prediction horizon expansion for MBPC of a 3‐level FCC are analyzed in a systematical way.

The analysis is mainly based on the mean square error (MSE) of current and capacitor voltage. The results are analysed for different lengths of the prediction horizon and for a wide range of weight factor values. Similarly the effect of a model simplification, neglecting the neutral point voltage, is studied when implementing MBPC for FCCs while considering the computational aspects. Validation of the simulation results is done by experiments on an FPGA‐based setup.

Including the effect of the neutral point voltage considerably increases the current control quality and a much wider range of good values for the weight factor exists. As this good range is not critically dependent on the current amplitude it is possible to select one weight factor value for all operating points. Furthermore, it is concluded that increasing the prediction horizon increases the computational load without improving the control quality.

The effects of increasing the prediction horizon when including other controlled variables is to be investigated, as well as the robustness to modeling errors. The MSE analysis methodology is very suitable for this further research.

For practitioners of MBPC in power electronics the paper proves that by means of simulations and the MSE one value for weight factor can be chosen for all operating points. The paper clearly shows that a practical implementation is feasible and demonstrates that neglecting the neutral point voltage is not good practice.

The MSE‐based analysis is shown to be a systematical and unbiased methodology to evaluate the effects of design choices. The results from this analysis can be directly applied in practical setups.

The natural control, feedback, stimuli and protection of these subsequent principles founded this project. Via properly conducted experiments, a multilayer computer rehabilitation system was created that integrated natural interaction assisted by electroencephalogram (EEG), which enabled the movements in the virtual environment and real wheelchair. For blind wheelchair operator patients, this paper involved of expounding the proper methodology. For educating the value of life and independence of blind wheelchair users, outcomes have proven that virtual reality (VR) with EEG signals has that potential.

Individuals face numerous challenges with many disorders, particularly when multiple dysfunctions are diagnosed and especially for visually effected wheelchair users. This scenario, in reality, creates in a degree of incapacity on the part of the wheelchair user in terms of performing simple activities. Based on their specific medical needs, confined patients are treated in a modified method. Independent navigation is secured for individuals with vision and motor disabilities. There is a necessity for communication which justifies the use of VR in this navigation situation. For the effective integration of locomotion besides, it must be under natural guidance. EEG, which uses random brain impulses, has made significant progress in the field of health. The custom of an automated audio announcement system modified to have the help of VR and EEG for the training of locomotion and individualized interaction of wheelchair users with visual disability is demonstrated in this study through an experiment. Enabling the patients who were otherwise deemed incapacitated to participate in social activities, as the aim was to have efficient connections.

To protect their life straightaway and to report all these disputes, the military system should have high speed, more precise portable prototype device for nursing the soldier health, recognition of solider location and report about health sharing system to the concerned system. Field programmable gate array (FPGA)-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals, the soldier’s health is observed on systematic bases. By emerging Verilog hardware description language (HDL) programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t the whole work is approved in a Vivado Design Suite. Classification of different abnormalities and cloud storage of EEG along with the type of abnormalities, artifact elimination, abnormalities identification based on feature extraction, exist in the segment of suggested architecture. Irregularity circumstances are noticed through developed prototype system and alert the physically challenged (PHC) individual via an audio announcement. An actual method for eradicating motion artifacts from EEG signals that have anomalies in the PHC person’s brain has been established, and the established system is a portable device that can deliver differences in brain signal variation intensity. Primarily the EEG signals can be taken and the undesirable artifact can be detached, later structures can be mined by discrete wavelet transform these are the two stages through which artifact deletion can be completed. The anomalies in signal can be noticed and recognized by using machine learning algorithms known as multirate support vector machine classifiers when the features have been extracted using a combination of hidden Markov model (HMM) and Gaussian mixture model (GMM). Intended for capable declaration about action taken by a blind person, these result signals are protected in storage devices and conveyed to the controller. Pretending daily motion schedules allows the pretentious EEG signals to be caught. Aimed at the validation of planned system, the database can be used and continued with numerous recorded signals of EEG. The projected strategy executes better in terms of re-storing theta, delta, alpha and beta complexes of the original EEG with less alteration and a higher signal to noise ratio (SNR) value of the EEG signal, which illustrates in the quantitative analysis. The projected method used Verilog HDL and MATLAB software for both formation and authorization of results to yield improved results. Since from the achieved results, it is initiated that 32% enhancement in SNR, 14% in mean squared error (MSE) and 65% enhancement in recognition of anomalies, hence design is effectively certified and proved for standard EEG signals data sets on FPGA.

The proposed system can be used in military applications as it is high speed and excellent precise in terms of identification of abnormality, the developed system is portable and very precise. FPGA-based soldier’s health observing and position gratitude system is proposed in this paper. Reliant on heart rate which is centered on EEG signals the soldier health is observed in systematic bases. The proposed system is developed using Verilog HDL programming language and executing on Artix-7 development FPGA board of part name XC7ACSG100t and synthesised using in Vivado Design Suite software tool.

Increasingly complex and sophisticated VLSI design, coupled with shrinking design cycles, requires shorter verification time and efficient debug method. Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. SOC HW/SW co‐verification technique seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. The purpose of this paper is to study a run‐time RTL debugging methodology for a FPGA‐based co‐verification system.

The debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI‐extended bus, instead of inserting extra scan‐chain logic, so the overhead for area is reduced.

This method provides internal nodes probing on an event‐driven co‐verification platform and achieves full observability for DUT. The experiment shows that, compared with a similar method, the area overhead for debug logic is reduced by 30‐50 per cent and compile time is shortened by 40‐70 per cent.

The proposed debugging technique achieves 100 per cent observability and can be applied to both RTL and gate‐level verification. The debugging tool is embedded into HDL simulator using Verilog VPI callback, so DUT signals are displayed together with testbench signals in the same waveform viewer. New value of DUT signal is read from FPGA whenever it changes, which allows run‐time debug.

With the rapid development of integrated circuits, verification of SOC chips has become a great challenge due to its integration and complexity. Traditional software‐based simulation methodology cannot meet verification needs. Therefore, FPGA‐based hardware acceleration technologies are requested in SOC verification. The classic methodology of hardware acceleration downloads the DUT (Device under Test) to the FPGA, while part of RTL codes and test bench is still run on the simulator in the workstation. Research found that the speed bottleneck of this methodology is mostly caused by the ping‐pong mode of data transmission between workstation software and the FPGA emulator, thus resulting in that channel transmission time takes too much proportion of total time. The purpose of this paper is to present a vector mode based hardware/software co‐emulation methodology, which leverages a pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel mechanism in that while user's design is under test in the emulator, signal data are transmitting in the channel simultaneously, thus increasing the speed of hardware acceleration and emulation.

The methodology of hardware acceleration proposed by this paper intercepts data for once from the emulation process of a traditional platform as test bench and utilizes direct memory access (DMA) channel to speed up data transfer, as well as increasing reasonable data caching mechanism, which reduces the ratio of channel transmission time in the entire emulation time, achieving accelerating emulation.

The proposed methodology and traditional hardware acceleration approach were tested on a quasi‐cyclic low‐density parity‐check (LDPC) decoder. Experiment results indicate that the proposed method can increase communication throughput 140 times compared with the traditional approach.

A vector mode based hardware/software co‐emulation methodology is presented in the paper. Higher communication throughput can be achieved by carrying out a parallel mechanism, as well as leveraging a pipeline structure to transmit, receive and buffer data.

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

The control of a quadrotor unmanned aerial vehicle (UAV) is a challenging problem because of its highly nonlinear dynamics, under-actuated nature and strong cross-couplings. To solve this problem, this paper aims to propose a robust control strategy, based on a concept of active disturbance rejection control (ADRC).

The altitude/attitude dynamics of a quadrotor is reformulated into the ADRC framework. Three distinct variations of the error-based ADRC algorithms, with different structures of generalized extended state observers (GESO), are derived for the altitude/attitude trajectory-following task. The convergence of the observation part is proved based on the singular perturbation theory. Through a frequency analysis and a quantitative comparison in a simulated environment, each design is shown to have certain advantages and disadvantages in terms of tracking accuracy and robustness. The digital prototypes of the proposed controllers for quadrotor altitude and attitude control channels are designed and validated through real-time hardware-in-the-loop (HIL) co-simulation, with field-programmable gate array (FPGA) hardware.

The effects of unavailable reference time-derivatives can be estimated by the ESO and rejected through the outer control loop. The higher order ESOs demonstrate better performances, but with reductions of stability margins. Time-domain simulation analysis reveals the benefits of the proposed control structure related to classical control approach. Real-time FPGA-based HIL co-simulations validated the performances of the considered digital controllers in typical quadrotor flight scenarios.

The conducted study forms a set of practical guidelines for end-users for selecting specific ADRC design for quadrotor control depending on the given control objective and work conditions. Furthermore, the paper presents detailed procedure for the design, simulation and validation of the embedded FPGA-based quadrotor control unit.

In light of the currently available literature on error-based ADRC, a comprehensive approach is applied here, which includes the design of error-based ADRC with different GESOs, its frequency-domain and time-domain analyses using different simulation of UAV flight scenarios, as well as its FPGA-based implementation and testing on the real hardware.

Deep learning techniques are unavoidable in a variety of domains such as health care, computer vision, cyber-security and so on. These algorithms demand high data transfers but require bottlenecks in achieving the high speed and low latency synchronization while being implemented in the real hardware architectures. Though direct memory access controller (DMAC) has gained a brighter light of research for achieving bulk data transfers, existing direct memory access (DMA) systems continue to face the challenges of achieving high-speed communication. The purpose of this study is to develop an adaptive-configured DMA architecture for bulk data transfer with high throughput and less time-delayed computation.

The proposed methodology consists of a heterogeneous computing system integrated with specialized hardware and software. For the hardware, the authors propose an field programmable gate array (FPGA)-based DMAC, which transfers the data to the graphics processing unit (GPU) using PCI-Express. The workload characterization technique is designed using Python software and is implementable for the advanced risk machine Cortex architecture with a suitable communication interface. This module offloads the input streams of data to the FPGA and initiates the FPGA for the control flow of data to the GPU that can achieve efficient processing.

This paper presents an evaluation of a configurable workload-based DMA controller for collecting the data from the input devices and concurrently applying it to the GPU architecture, bypassing the hardware and software extraneous copies and bottlenecks via PCI Express. It also investigates the usage of adaptive DMA memory buffer allocation and workload characterization techniques. The proposed DMA architecture is compared with the other existing DMA architectures in which the performance of the proposed DMAC outperforms traditional DMA by achieving 96% throughput and 50% less latency synchronization.

The proposed gated recurrent unit has produced 95.6% accuracy in characterization of the workloads into heavy, medium and normal. The proposed model has outperformed the other algorithms and proves its strength for workload characterization.

The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.

An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.

FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm² of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.

The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

The purpose of this paper is to describe an innovative compliance control architecture for hybrid multi‐legged robots. The approach was verified on the hybrid legged‐wheeled robot ASGUARD, which was inspired by quadruped animals. The adaptive compliance controller allows the system to cope with a variety of stairs, very rough terrain, and is also able to move with high velocity on flat ground without changing the control parameters.

The paper shows how this adaptivity results in a versatile controller for hybrid legged‐wheeled robots. For the locomotion control we use an adaptive model of motion pattern generators. The control approach takes into account the proprioceptive information of the torques, which are applied on the legs. The controller itself is embedded on a FPGA‐based, custom designed motor control board. An additional proprioceptive inclination feedback is used to make the same controller more robust in terms of stair‐climbing capabilities.

The robot is well suited for disaster mitigation as well as for urban search and rescue missions, where it is often necessary to place sensors or cameras into dangerous or inaccessible areas to get a better situation awareness for the rescue personnel, before they enter a possibly dangerous area. A rugged, waterproof and dust‐proof corpus and the ability to swim are additional features of the robot.

Contrary to existing approaches, a pre‐defined walking pattern for stair‐climbing was not used, but an adaptive approach based only on internal sensor information. In contrast to many other walking pattern based robots, the direct proprioceptive feedback was used in order to modify the internal control loop, thus adapting the compliance of each leg on‐line.