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These implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.

This paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.

The variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.

The simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

Describes Actel’s programmable technology. Early adopters of this technology, in both Europe and North America in experimental and telecommunication space programmes used these field programmable gate arrays (FPGAs) very successfully. Owing to the success of these early adopters, Actel transferred its technology to a radiation hardened wafer fab and now offers a rad hard version of its commercial product, serving the needs of the traditional government end use space market and long lifetime missions. Since the introduction of the rad hard FPGAs the industry has undergone major shifts in attitudes. While there is still a significant demand for radiation hardened devices, lower cost alternatives with a lower level of radiation tolerance are expected to exist in the majority of space programmes.

This paper aims to examine the design and control of a symmetric multilevel inverter (MLI) using grey wolf optimization and differential evolution algorithms.

The optimal modulation index along with the switching angles are calculated for an 11 level inverter. Harmonics are used to estimate the quality of output voltage and measuring the improvement of the power quality.

The simulation is carried out in MATLAB/Simulink for 11 levels of symmetric MLI and compared with the conventional inverter design. A solar photovoltaic array-based experimental setup is considered to provide the input for symmetric MLI. Field Programmable Gate Array (FPGA) based controller is used to provide the switching pulses for the inverter switches.

Attempted to develop a system with different optimization techniques.

The conventional two-level inverter suffers from harmonics, higher direct current (DC) link voltage requirement, higher dv/dt and heating of the rotor. This study aims to overcome by using a multilevel inverter for brushless DC (BLDC) drive.

This paper presents a comparative analysis of the conventional two-level and three-level multilevel inverter for electric vehicle (EV) application using BLDC drive.

A three-level Active Neutral Point Clamped Multilevel inverter (ANPCMLI) is proposed in this paper which provides DC link voltage control. Simulation studies of the multilevel inverter and BLDC motor is carried out in MATLAB.

The ANPCMLI fed BLDC simulation results shows that there is the significant reduction in the BLDC motor torque ripple, switching stress and harmonic distortion in the BLDC motor fed ANPCMLI compared to the conventional two-level inverter. A prototype of ANPCMLI fed BLDC drive along with field programmable gate array (FPGA) control is built and MATLAB simulation results are verified experimentally.

The aim of this work is to examine the Hopfield network for the field programmable gate array (FPGA) cell placement.

Implementation of an algorithm in FPGA circuits requires synthesis, placement and the routing of logic cells. The placement takes the longest time for computation. Therefore, an algorithm for a run‐time reconfigurable system can be chosen from among earlier prepared algorithms. This paper presents a Hopfield neural network for solving the placement problem. The Hopfield network was also used for processing units in a parallel placement. Hardware implementation of presented solutions could accelerate the FPGA placement by orders of magnitude in comparison with placers executed on traditional computers. Hardware accelerators could also be applied to the design of other VLSI circuits. The simulation results for the FPGA placement are presented.

The Hopfield network and parallel placement give comparable placements with the method using a simulated annealing algorithm. The parallel placement enables a decrease in total number of neurons and neuron connections which are necessary for simultaneous placement of all cells in a circuit.

This work provides a starting‐point for further research under hardware realization of the cell placement by using the Hopfield network. The presented solutions can be used for FPGA, gate array, sea‐of‐gates circuits and standard cell circuits with the same size cells.

The Hopfield network is used for placement in real circuits, in which nets contain multiple terminals, and for processing units in a parallel placement.

This paper proposes a design of an efficient and automated experimental platform for frequency modulated continuous wave (FMCW) radars. The platform can quickly flexibly generate the waveform that meets measurement requirements and significantly improve experimental efficiency.

This platform not only includes radio frequency devices but also integrates a programmable transmitter based on field programmable gate array. By configuring the waveform data, the experimental platform can generate waveforms with adjustable parameters and realize automatic emission, reception and processing of signals. Different from traditional fast Fourier transform, this paper uses a discrete-time Fourier transform to process low-frequency signals to get more accurate results.

The authors demonstrate the effectiveness of the platform through a single-path cable experiment, an indoor ranging experiment by using different modulating waveforms and a speed measurement experiment. With complete functions and strong flexibility, the platform can operate effectively in various conditions and greatly improve the efficiency of research and study.

The platform can accelerate the research studies and applications of FMCW radars in the fields of automatic drive, through-wall detection and health-care applications.

Cost and functionality are taken into account in the platform, which can significantly improve the efficiency of research. The proposed signal processing method improves the accuracy while its computation complexity does not increase significantly.

The purpose of this paper is to integrate the function of a speed controller for induction motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator, the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital converter interface circuit, etc. into one field programmable gate array (FPGA).

First, the mathematical modeling of an IM drive, the field-oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based on electronic design automation simulator link, a co-simulation work constructed by ModelSim and Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties (IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the IM drive.

In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time to complete the computation of the PI controller, the slip speed estimator, the current vector controller are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.

Fast computation in FPGA can speed up the speed response of IM drive system to increase the running performance.

This is the first time to realize all the function of a speed controller for IM drive within one FPGA.

The purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement.

In this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number.

The performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented.

The presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.