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This paper aims to report small-signal parameter extraction and simulation of enhanced dual-channel dual-material gate AlGaN/GaN high electron mobility transistor (HEMT) for the first time for the characterization of a device in microwave range of frequency.

For parameter extraction, a standard and well-known direct parameter extraction methodology is applied. Extrinsic elements of small-signal circuit model are extracted from measured S-parameters obtained using pinch-off cold field effect transistor (FET) biasing in the first step at a low frequency range and at a higher frequency range in the second step to ensure higher extraction accuracy. Intrinsic elements are extracted from intrinsic Y-parameters that are obtained after de-embedding all the extrinsic parasitic elements of the device. Figure of merits of radio frequency are also derived from the measured results and S-parameters of the proposed device.

Small signal parameters of the proposed device circuit model are extracted using the standard direct parameter extraction technique. Analysis of microwave figure of merits for device include maximum oscillation frequency, cut-off frequency, current gain, transducer power gain, available power gain, maximum stable gain, transconductance, drain conductance, stern stability factor and time delay.

The paper bridges the gaps between theory and experimental practices by validating extracted results with reported results of structurally matching devices.

An enhanced device structure investigated for small signal parameters incorporates field plate over dual metal engineered gate to provide better electric field uniformity, effective suppression of short channel effect, reduction in current collapse, improvement in carrier transport efficiency and enhancement in drain current capabilities.

The purpose of this paper is to present an improved model based on center potential instead of surface potential which is physically more relevant and accurate. Also, additional analytic insights have been provided to make the model independent and robust so that it can be extended to a full range compact model.

The design methodology used is center potential based analytical modeling using Psuedo-2D Poisson equation, with ingeniously developed boundary conditions, which help achieve reasonably accurate results. Also, the depletion width calculation has been suitably remodeled, to account for proper physical insights and accuracy.

The proposed model has considerable accuracy and is able to correctly predict most of the physical phenomena occurring inside the broken gate Tunnel FET structure. Also, a good match has been observed between the modeled data and the simulation results. I_on/I_ambipolar ratio of 10^(−8) has been achieved which is quintessential for low power SOCs.

The modeling approach used is different from the previously used techniques and uses indigenous boundary conditions. Also, the current model developed has been significantly altered, using very simple but intuitive technique instead of complex mathematical approach.

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.

This model correctly predicts the output characteristics, I_DS−V_GS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.

Can be implemented in a SPICE like simulator for studying circuit behaviour containing strained‐Si/SiGe bulk MOSFETs.

The model discussed in this paper can be easily implemented in a circuit simulator and used for the characterization of strained silicon devices. This complements the recent trend of investigation of new materials and device structures to maintain the rate of advancement in VLSI technology.

This paper presents, for the first time, a compact surface potential‐based analytical model for strained‐Si/SiGe MOSFETs which predicts the device characteristics reasonably well over their range of operation.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.