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This study aims to develop a compact analytical models for undoped symmetric double-gate MOSFET based on carrier approach. Double-Gate (DG) MOSFET is a newly emerging device that can potentially further scale down CMOS technology owing to its excellent control of short channel effects, ideal subthreshold slope and free dopant-associated fluctuation effects. DG MOSFET is of two types: the symmetric DG MOSFET with two gates of identical work functions and asymmetric DG MOSFET with two gates of different work functions. To fully exploit the benefits of DG MOSFETs, the body of DG MOSFETs is usually undoped because the undoped body greatly reduces source and drain junction capacitances, which enhances the switching speed. Highly accurate and compact models, which are at the same time computationally efficient, are required for proper modeling of DG MOSFETs.

This paper presents a carrier-based approach to develop a compact analytical model for the channel potential, threshold voltage and drain current of a long channel undoped symmetric DG MOSFETs. The formulation starts from a solution of the 2-D Poisson’s equation in which mobile charge term has been included. The 2-D Poisson’s equation in rectangular coordinate system has been solved by splitting the total potential into long-channel (1-D Poisson’s equation) and short-channel components (remnant 2-D differential equation) in accordance to the device physics. The analytical model of the channel potential has been derived using Boltzmann’s statistics and carrier-based approach.

It is shown that the metal gate suppresses the center potential more than the poly gate. The threshold voltage increases with increasing metal work function. The results of the proposed models have been validated against the Technology Computer Aided Design simulation results with close agreement.

Compact Analytical models for undoped symmetric double gate MOSFETs.

The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.

This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.

The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.

The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

As the physical dimensions of the devices are reduced to the submicrometer regime, the hot‐carrier reliability has become an important issue in the scaling of the p‐MOSFET as well as the n‐MOSFET. In this paper, we present a unified approach for p‐MOSFET degradation due to the trapping of the hot electrons in the gate oxide layers. A physical analytical model, based on the pseudo two‐dimensional model, is derived for the first time to describe the linear and saturation drain current degradation. The model has been verified by comparing the calculation and the measurement from submicron p‐MOSFET's with different channel lengths and oxide thickness. There are no empirical parameters in the model. Two physical parameters: the capture cross section and the density of states of electron traps, which can be determined independently from the measured degradation characteristics, are valid for both the linear current and the saturation current degradation. The simple expression is very suitable for the predicting of the circuit reliability.

This paper aims to describe the fabrication and characterization of current mirror-integrated microelectromechanical systems (MEMS)-based pressure sensor.

The integrated pressure-sensing structure consists of three identical 100-µm long and 500-µm wide n-channel MOSFETs connected in a resistive loaded current mirror configuration. The input transistor of the mirror acts as a constant current source MOSFET and the output transistors are the stress sensing MOSFETs embedded near the fixed edge and at the center of a square silicon diaphragm to sense tensile and compressive stresses, respectively, developed under applied pressure. The current mirror circuit was fabricated using standard polysilicon gate complementary metal oxide semiconductor (CMOS) technology on the front side of the silicon wafer and the flexible pressure sensing square silicon diaphragm, with a length of 1,050 µm and width of 88 µm, was formed by bulk micromachining process using tetramethylammonium hydroxide solution on the backside of the wafer. The pressure is monitored by the acquisition of drain voltages of the pressure sensing MOSFETs placed near the fixed edge and at the center of the diaphragm.

The current mirror-integrated pressure sensor was successfully fabricated and tested using in-house developed pressure measurement system. The pressure sensitivity of the tested sensor was found to be approximately 0.3 mV/psi (or 44.6 mV/MPa) for pressure range of 0 to 100 psi. In addition, the pressure sensor was also simulated using Intellisuite MEMS Software and simulated pressure sensitivity of the sensor was found to be approximately 53.6 mV/MPa. The simulated and measured pressure sensitivities of the pressure sensor are in close agreement.

The work reported in this paper validates the use of MOSFETs connected in current mirror configuration for the measurement of tensile and compressive stresses developed in a silicon diaphragm under applied pressure. This current mirror readout circuitry integrated with MEMS pressure-sensing structure is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

This paper aims to characterize the relationship between the interelectrode capacitance (C) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and the applied bias voltage (V) by a fractional-order equivalent model.

A Riemann–Liouville-type fractional-order equivalent model is proposed for the C–V characteristic of MOSFETs, which is based on the mathematical relationship between fractional calculus and the semiconductor physical model for the interelectrode capacitance of metal oxide semiconductor structure. The C–V characteristic data of an N-channel MOSFET are obtained by Silvaco TCAD simulation. A differential evolution-based offline scheme is exploited for the parameter identification of the proposed model.

According to the results of theoretical analysis, mathematical derivation, simulation and comparison, this paper illustrates that, along with the variation of bias voltage applied, the interelectrode capacitance (C) of MOSFETs performs a fractional-order characteristic.

This work uncovers the fractional-order characteristic of MOSFETs’ interelectrode capacitance. By the proposed model, the influence of doping concentration on the gate leakage parasitic capacitance of MOSFETs can be revealed. In the pre-defined doping concentration range, the relative error of the proposed model is less than 5% for the description of C–V characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). Compared to some existing models, the proposed model has advantages in both model accuracy and model complexity, and the variation of model parameters can directly reflect the relationship between the characteristics of MOSFETs and the doping concentration of materials. Accordingly, the proposed model can be used for the microcosmic mechanism analysis of MOSFETs. The results of the analysis produce evidence for the widespread existence of fractional-order characteristics in the physical world.

To use the 4H-SiC material in integrated circuits for high temperature application, an accurate and simple circuit model of n-channel planar 4H-SiC MOSFET is required.

In this paper, a SPICE model of n-channel planar 4H-SiC MOSFET was built based on the device simulation results and measurement results. Firstly, a device model was simulated with Sentaurus TCAD, with measured parameters from fabricated planar 4H-SiC MOSFET previously. Then the device simulation results were analyzed and parameters for SPICE models were extracted. With these parameters, an accurate SPICE model was built and simulated.

The SPICE model exhibits the same performance as the measured results with different environment temperatures. The simulation results indicate that the maximum fitting error is 0.22 mA (7.33% approximately) at 200 °C. A common-source amplifier with this model is also simulated and the simulated gain is stable at different environment temperatures.

This paper provides a reliable modeling method for n-Channel Planar 4H-SiC MOSFET and reference value for the design of 4H-SiC high temperature integrated circuit.

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.

This model correctly predicts the output characteristics, I_DS−V_GS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.

Can be implemented in a SPICE like simulator for studying circuit behaviour containing strained‐Si/SiGe bulk MOSFETs.

The model discussed in this paper can be easily implemented in a circuit simulator and used for the characterization of strained silicon devices. This complements the recent trend of investigation of new materials and device structures to maintain the rate of advancement in VLSI technology.

This paper presents, for the first time, a compact surface potential‐based analytical model for strained‐Si/SiGe MOSFETs which predicts the device characteristics reasonably well over their range of operation.

This paper aims to describe the fabrication, packaging and testing of a resistive loaded p-channel metal-oxide-semiconductor field-effect transistor-based (MOSFET-based) current mirror-integrated pressure transducer.

Using the concept of piezoresistive effect in a MOSFET, three identical p-channel MOSFETs connected in current mirror configuration have been designed and fabricated using the standard polysilicon gate process and microelectromechanical system (MEMS) techniques for pressure sensing application. The channel length and width of the p-channel MOSFETs are 100 µm and 500 µm, respectively. The MOSFET M1 of the current mirror is the reference transistor that acts as the constant current source. MOSFETs M2 and M3 are the pressure-sensing transistors embedded on the diaphragm near the mid of fixed edge and at the center of the square diaphragm, respectively, to experience both the tensile and compressive stress developed due to externally applied input pressure. A flexible square diaphragm having a length of approximately 1,000 µm and thickness of 50 µm has been realized using deep-reactive ion etching of silicon on the backside of the wafer. Then, the fabricated sensor chip has been diced and mounted on a TO8 header for the testing with pressure.

The experimental result of the pressure sensor chip shows a sensitivity of approximately 0.2162 mV/psi (31.35 mV/MPa) for an input pressure of 0-100 psi. The output response shows a good linearity and very low-pressure hysteresis. In addition, the pressure-sensing structure has been simulated using the parameters of the fabricated pressure sensor and from the simulation result a pressure sensitivity of approximately 0.2283 mV/psi (33.11 mV/MPa) has been observed for input pressure ranging from 0 to 100 psi with a step size of 10 psi. The simulated and experimentally tested pressure sensitivities of the pressure sensor are in close agreement with each other.

This current mirror readout circuit-based MEMS pressure sensor is new and fully compatible to standard CMOS processes and has a promising application in the development CMOS-MEMS-integrated smart sensors.

The purpose of this paper is to present an analytical model and simulation for cylindrical gate all around MOSFTEs including quantum effects.

To incorporating the impact of quantum effects, the authors have used variational method for solving the Poisson and Schrodinger equations. The accuracy of the results obtained using this model is verified by comparing them with simulation results.

This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge centroid, threshold voltage, inversion charge, gate capacitance and drain current. The calculated expressions for the above parameters are simple and accurate. The validity of this model was checked for the devices with different dimensions and bias voltages.

Simulation based on the compact physical models reduces the cost of developing a sophisticated fabrication technology and shortens the time-to-market. They may also be utilized to explore innovative device structures.

This paper presents, for the first time, a compact quantum analytical model for cylindrical surrounding gate MOSFETs which predicts the device characteristics reasonably well over the entire range of device operation (above threshold as well as sub-threshold region).

The aim of this paper is to present non-destructive and destructive methods of failure analysis of epoxy moulded IC packages on the example of power MOSFETs in SOT-227 package.

A power MOSFET in SOT-227 package was examined twice using X-ray inspection, at first as the whole component to check if it is damaged and then after removing the upper part of package by mechanical grinding. The purpose of the second X-ray inspection was to prepare images for estimation of the total number and approximate location of voids in soft solder layers. Finally, power MOSFETs were subjected to decapsulation process using a concentrated sulphuric acid to verify existence of damage areas noticed during X-ray analysis and to observe other possible failures such as cracks in aluminium metallization or wires deformation.

X-ray analysis was revealed to be adequate technique to detect damage (e.g. meltings) in power MOSFETs in SOT-227 package, but only when tested components were analysed in the side view. This type of analysis combined with a graphic software is also suitable for voids estimation in soft solder layers. Moreover, it was found that a single acid (concentrated sulphuric acid) at elevated temperature can be successfully used for decapsulation of power MOSFETs in SOT-227 package without damage of aluminium metallization and aluminium wires. Such decapsulation process enables analysis of defects in wire, die and package materials.

Further investigations are required to examine if the presented methods of failures analysis can be used for other types of components (e.g. high power resistors) in similar packages.

The described methods of failure analysis can find application in electronic industry to select components which are free of damage and in effect which allow to produce high reliable devices. Apart from it, the presented method is applicable to evaluate reasons of improper work of tested electronic devices and to identify faked components.

This paper contains valuable information for research and technical staff involved in the assessment of electronic devices who needs practical methods of failure analysis of epoxy moulded IC packages.