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The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.

Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.

This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.

All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

The purpose of this paper is to propose a time‐dependent mobility degradation model which is independent from the process or operating conditions.

In total, four transistors under test are electrically stressed using constant positive electrical stress voltage technique with the gate bias of V_G=40 V DC, where the source and drain were grounded. The authors increased the stress voltage step by step to avoid electrostatic discharge and recorded the I_D‐V_DS and I_D‐V_GS measurements in time intervals during the stress.

The experimental results show that the output current and the threshold voltage of the transistor are increased after the stress. Mobility and channel length are decreased. The changes in the transistor parameters were associated to interface state Si/SiO₂ effects. The authors used the physical changes in transistor and proposed a new‐time dependent mobility degradation model. The mobility change was calculated using the proposed model and compared with the experimental results. It was seen that the calculated and experimental results are in good agreement.

This is an original research paper and enables the mobility degradation to be predicted independently from effects of process or operational changes such as oxide thickness, substrate doping, and applied voltages on transistor.

The purpose of this paper is to develop a method for multiple soft fault diagnosis of nonlinear circuits including fault detection, identification of faulty elements and estimation of their values in real circumstances.

The method for fault diagnosis proposed here uses a measurement test leading to a system of nonlinear equations expressing the measured quantities in terms of the circuit parameters. Nonlinear functions, which appear in these equations are not given in explicit analytical form. The equations are solved using a homotopy concept. A key problem of the solvability of the equations is considered locally while tracing the solution path. Actual faults are selected on the basis of the observation that the probability of faults in fewer number of elements is greater than in a larger number of elements.

The results indicate that the method is an effective tool for testing nonlinear circuits including bipolar junction transistors and junction field effect transistors.

The homotopy method is generalized and associated with a restart procedure and a numerical algorithm for solving differential equations. Testable sets of elements are found using the singular value decomposition. The procedure for selecting faulty elements, based on the minimal fault number rule, is developed. The method comprises both theoretical and practical aspects of fault diagnosis.

Biosensors have been described as a synergistic combination of biochemistry and microelectronics.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

An overview of the concerns involved in the operation of electronic hardware at elevated temperatures is presented. Materials selection and package design issues are addressed for a wide range of packaging elements from the semiconductor chip to the box. It is found that most elements of common high density device and packaging architecture can be used up to 200°C. However, gold‐aluminium wirebonds, eutectic tin‐lead solder joints and die attaches, and FR‐4 boards will seriously degrade at temperatures below 200°C. For these elements, alternative materials of construction are recommended. Comparisons are made between package design for high power dissipation and that for high temperature operation.

The Monte‐Carlo particle model is a technique of simulating small semiconductor devices. It consists briefly of following the detailed transport histories of individual carriers, their time of free flight and consequent scattering chosen by a random number technique. A description of the method is given. The method has proved itself successful in semiconductor analysis, and as an example of its application we are using it to study the influence the epitaxial doping has on the performance of field‐effect transistors. We are comparing a transistor with an epitaxially grown active layer, with one with an ion implanted active layer and with an ideal device with an abrupt transition between the epilayer and the substrate. The cut‐off bias for ideal transistor is found to be more sharply defined than for the other two types of transistors. The spatial distribution of the carriers follows roughly the doping profile near the source. Underneath the gate the peak of the carrier density is pushed further down and into the substrate as the gate bias increases. This peak also weakens as the gate bias rises, and vanishes at, and beyond cut‐off. In the high field region after the gate the upper valleys population increases with increased drain bias and decreases with increased gate bias. The power gain and the y‐parameters are examined for all devices, both near pinch‐off and for no external gate bias. In both cases the ion implanted transistor shows the greatest gain. This transistor also exhibits the lowest minimum noise figure.

An simple model for the simulation of the electrical behaviour of several types of junction controlled field‐effect transistors is proposed. It is based on the calculation of the carrier concentration in the channel by means of a self‐consistent solution of Schrödinger and Poisson's equation in the direction perpendicular to the current flow. Based on the carrier concentration the dc, the small‐signal, and also the noise properties of the devices may be simulated. The calculated characteristics of a sub‐quarter micron gate GaAs MESFET, a δ‐doped GaAs FET and a Velocity Modulation Transistor will be presented and discussed.

Numerically simulating the behavior of GaAs devices requires a model for the distorted densities of states, band edge shifts, ΔΕc and ΔΕv, and effective intrinsic carrier concentrations, nie. The subscripts c and v denote the conduction and valence bands, respectively. Klauder's self‐energy methods (third‐level and fifth‐level) are applied to calculate the effects of carrier‐dopant ion interactions on the densities of states for GaAs. The effects of carrier‐carrier interactions have been calculated according to the theory of Abram et al. modified for 300 K. These calculations span most of the range of densities encountered in GaAs devices. This range is 5 × 1016 cm−3 to 1019 cm−3 for n‐type GaAs and from 1018 cm−3 to 1020 cm−3 for p‐type GaAs. We present in this paper theoretical data on how ΔΕc, ΔΕv, and nie vary with dopant densities. The variations with dopant and/or carrier densities of the distorted densities of states, Fermi energies screening radii, and first Born shifts will be given in a future publication.