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Analytical drain current model for nanoscale strained‐Si/SiGe MOSFETs

Himanshu Batwani (Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India)
Mayank Gaur (Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India)
M. Jagadesh Kumar (Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India)

Abstract

Purpose

The purpose of this paper is to present an analytical drain current model for output characteristics of strained‐Si/SiGe bulk MOSFET.

Design/methodology/approach

A physics‐based model for current output characteristics and transconductance of strained‐Si/SiGe bulk devices has been developed incorporating the impact of strain (in terms of equivalent Ge mole fraction), strained silicon thin film thickness, gate work function, channel length and other device parameters. The accuracy of the results obtained using this model is verified by comparing them with 2D device simulations.

Findings

This model correctly predicts the output characteristics, IDSVGS characteristics, transconductance and output conductance of the strained‐Si/SiGe MOSFET and demonstrates a significant enhancement in the drain current of the MOSFET with increasing strain in the strained‐Si thin film, i.e. with increasing equivalent Ge concentration in the SiGe bulk.

Research limitations/implications

Can be implemented in a SPICE like simulator for studying circuit behaviour containing strained‐Si/SiGe bulk MOSFETs.

Practical implications

The model discussed in this paper can be easily implemented in a circuit simulator and used for the characterization of strained silicon devices. This complements the recent trend of investigation of new materials and device structures to maintain the rate of advancement in VLSI technology.

Originality/value

This paper presents, for the first time, a compact surface potential‐based analytical model for strained‐Si/SiGe MOSFETs which predicts the device characteristics reasonably well over their range of operation.

Keywords

Citation

Batwani, H., Gaur, M. and Jagadesh Kumar, M. (2009), "Analytical drain current model for nanoscale strained‐Si/SiGe MOSFETs", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 28 No. 2, pp. 353-371. https://doi.org/10.1108/03321640910929263

Publisher

:

Emerald Group Publishing Limited

Copyright © 2009, Emerald Group Publishing Limited

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