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To achieve integration of chip scale package (CSP) devices into main stream surface mount technology (SMT) assembly, various experiments have been required. In process development, experiences learned from flip chip attach and ball grid array (BGA) assembly were utilized. Key process parameters for CSP assembly were defined and some of those key factors were optimized. They will be presented in this paper. Some observations during prototype build have been documented for correlation with reliability results in the future. The requirements for further CSP assembly studies will also be addressed in this paper.

This paper addresses the issues involved in the design of high‐density boards for high‐density chip scale packages. An analytical model is developed to calculate the number of I/Os accommodated by the printed wiring board. The model is placed under constraints of package area, package I/O pitch, number of lanes per channel, PWB device feature sizes (I/O, via pad, signal traces), number of routing layers on board and the partition of routing regions on each level. The model is utilized to study the precise impact of number of routing layers and device feature size on the I/O density of PCB. The scheme for optimally partitioning each layer to achieve maximum I/O density is discussed. Specific guidelines are provided pertaining to the usage of higher board layers and/or reduced device feature sizes to design high‐density boards for future electronic products.

New developments in the semi‐conductor industry lead to higher I/O counts. Packaging is changing to new, smaller packages, like TCPs and CSPs, and the pitch density increases as well. For the fanout of such pages on the PCB, new design rules have to be applied. Blind via holes, sequential build‐up technologies, new ways to form holes, new materials, a lot of questions for the PCB manufacturer. The integration of passive components, such as bypass capacitors and pull up and pull down resistors, into the PCB, go along with the next generation of packaging technology. This adds complexity to the printed circuit boards, leading to a new generation of PCBs that could better be called Integrated Component Boards (ICB). These boards offer a much higher price/area for the PCB manufacturer and at the same time give the OEM better performance with fewer assembly steps and much smaller units.

High‐density packaging devices have unique characteristics which make their assembly, test and repair very difficult. The only realistic method of rework is to replace the defective component with a new or re‐balled component. Although a wide range of rework techniques is available, degradation in assembly reliability may accompany the process. The formation of brittle secondary intermetallic compounds following CSP rework can adversely affect the mechanical properties of the joint, particularly when they make up a significant proportion of its thickness. Reports on the effects of different CSP rework techniques on intermetallic layer formation. Two PCB pad‐cleaning methods and three flux/paste deposition methods are investigated. The reworked joints are analysed using optical microscopy to determine the extent of intermetallic growth. Their quality is also assessed using shear strength testing prior to, and after, thermal ageing at 1008C to accelerate the growth of intermetallic compounds and evolution of the solder grain structure.

As part of a programme of characterisation of interconnection technologies for computer server products the present investigation was conducted to determine the attachment integrity and long‐term reliability of resistor network ceramic Chip Scale Package (CSP) solder joints. Accelerated thermal cycling with electrical continuity monitoring of the solder joints was used to determine reliability. The thermal cycling was combined with metallographic examination of appropriate solder joints to evaluate the failure modes and to corroborate the failure thresholds. The measured reliability for the CSP solder joints was 1,027 thermal cycles. This implied an estimated minimum lifetime of 7.8 years for the product in a worst‐case field use. The reliability was virtually unaffected by the solder joint pad size and geometry on the board. All fatigue failed solder joints exhibited similar failure modes.

In this paper, a computational analysis is presented for the comparison of wafer level chip scale package‐on‐build‐up PCB assemblies with various solders and microvia configurations. The printed circuit board of the assembly has one build‐up layer on one side. For comparison, the board with two build‐up layers on the same side is studied as well. Furthermore, two solder joint materials, namely, 62Sn–2Ag–36Pb and 96.5Sn–3.5Ag are studied for comparison. The assembly is simulated by a finite element model and the model is analyzed under thermal cyclic loading. A comprehensive stress analysis is performed and comparisons are made for assembly deformation, stress/strain ranges, and creep responses.

This paper describes the methodology used to evaluate several different stencil fabrication methods, aperture sizes and thicknesses and different solder pastes. Data collected included the number of printing defects and measurement of solder paste volume and height. Statistics have been used for the analysis of quantitative data. Results from this evaluation have been critical in the success of a new process for CSP assembly in a standard SMT environment. Stencil designs and solder paste selection for other applications have also benefited from the conclusions of this study.

The explosive growth of high‐density packaging has created a tremendous impact on the electronics assembly and manufacturing industry. Ball Grid Array (BGA), Chip Scale Packaging (CSP), Direct Chip Attach (DCA), and flip‐chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. In this paper, they will be briefly discussed.

CSP (chip scale packaging) and flip chip area array technologies are emerging within the electronics packaging industry to provide solutions capable of fulfilling the technological demands of computer, telecom and consumer electronic products. However, the full potential of area array attach can only be realised if the next level of interconnect is capable of supporting the fine pitch and high I/O characteristics of emerging CSP and flip chip technology. Celestica has addressed this issue by investigating next generation printed circuit board (PCB) technology, to assess the capability of organic based laminate as a high density interconnect. This paper describes the manufacturing experiments performed to produce a laser microvia interconnect solution. The mechanical performance of the interconnect is also presented to confirm its compatibility with area array assembly.