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This article comprises Chapter 6 from the recently published book ‘An Engineer’s Guide to Flexible Circuit Technology by J. Fjelstad

The purpose of this paper is to introduce several synchronization test methods of Network‐on‐Chip (NoC) at multi‐clock domains by digital logic circuits.

First, the authors gave the structure of NoC, the test methods for NoC in multi‐clock domains, including Built‐in Self Test (BIST) structure and the architecture of embedded core test. Then the authors approached four different synchronization structures: two‐level trigger, two kinds of lock methods, toggle and pulse synchronization methods. Based on the NoC work conditions, the authors built the experiment structures of different methods, and obtained the experiment results at high frequencies.

From the experiments at high frequency, it can be seen that the methods of toggle and the pulse methods are prone to failed synchronization. Therefore, the lock method is more appropriate for NoC under multiple clock domains.

In this paper, several synchronization test methods of NoC at multi‐clock domains are discussed and compared, and the best one determined.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

Interlaminar short circuits in turbo generator stators can lead to local damage of the iron core. The purpose of this paper is to model an interlaminar short circuit diagnosis test on an existing structure.

This work presents the modeling of short‐circuited laminations in a stator yoke of a turbo‐generator. A 3D finite element model, associated to a homogenization technique, is used to calculate the short‐circuit current. The diagnosis test known as El Cid has been modelled as well.

Calculation results are compared with the experiment. The same tendency has been observed both in experimental and numerical results.

Additional calculations may be performed (parametric studies) in order to investigate El Cid measuring under different conditions (different material properties, fault position, size), which may lead to a better interpretation of the results.

Modelling of short circuit diagnosis tests under different conditions may help with the interpretation of measuring results, predicting the fault size/seriousness and location. So, only the concerned parts of the stator have to be disassembled and repaired/rebuilt.

It is not easy to model numerically a structure with a short circuit inside, since different dimensions are involved: the fault and the varnish between laminations are much smaller than the stator itself. Thus, homogenization techniques have been used to model the lamination stack region. The combination of this technique with the modelling of the El Cid test constitutes a tool to study this kind of fault and calculate its severity and location in a stator.

In view of the uncertainty of the applicability of traditional ionic contamination measurement to surface mount assemblies, a mathematical study was made of the phenomena involved. A model was derived, showing that under‐component contamination behaves differently from ordinary surface contamination. By breaking down a curve obtained under practical conditions into its components, it is therefore possible to derive separate figures for surface and under‐component ionic contamination, ignoring the influence of spurious noise signals. A new software, using these techniques, has been written for this application. Comparative tests between non‐destructive testing, using this software, and tests on similar circuits with the components torn off, show that there is a close correlation between the results from these two techniques, even though the under‐component contamination is only partially dissolved with the former method.

A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

This paper, which will be published in two parts in consecutive issues of Circuit World, reproduces a chapter of the recently published book ‘Handbook of Printed Circuit Technology: New Processes, New Technologies’, edited by G. Herrmann and K. Egerer and published by Electrochemical Publications Ltd, Port Erin, Isle of Man.

The purpose of this paper is to provide the high-pass (HP) negative group delay (NGD) circuit based (RL) network. Synthesis and experimental investigation of HP-NGD circuit are developed.

The research work methodology is organized in three phases. The definition of the HP-NGD ideal specifications is introduced. The synthesis method allowing to determine the RL elements is developed. The validation results are discussed with comparison between the calculated model, simulation and measurement.

This paper shows a validation of the HP-NGD theory with responses confirming NGD optimal frequency, value and attenuation of about (9 kHz, −1.12 µs, −1.64 dB) and (21 kHz, −0.92 µs, −4.81 dB) are measured. The tested circuits have experimented NGD cut-off frequencies around 5 and 11.7 kHz.

The validity of the HP-NGD topology depends on the coil self-inductance resonance. The HP-NGD effect is susceptible to be penalized by the parasitic elements of the self.

The NGD circuit is usefully exploited in the electronic and communication system to reduce the undesired delay effect context. The NGD can be used to compensate the delay in any electronic devices and system.

Applications based on the NGD technology will be helpful in the communication, transportation and security research fields by reducing the delay inherent to any electronic circuit.

The originality of the paper concerns the synthesis formulations of the RL elements in function of the expected HP-NGD optimal frequency, value and attenuation. In addition, an original measurement technique of HP-NGD is also introduced.

The purpose of this paper is to develop a method for multiple soft fault diagnosis of nonlinear circuits including fault detection, identification of faulty elements and estimation of their values in real circumstances.

The method for fault diagnosis proposed here uses a measurement test leading to a system of nonlinear equations expressing the measured quantities in terms of the circuit parameters. Nonlinear functions, which appear in these equations are not given in explicit analytical form. The equations are solved using a homotopy concept. A key problem of the solvability of the equations is considered locally while tracing the solution path. Actual faults are selected on the basis of the observation that the probability of faults in fewer number of elements is greater than in a larger number of elements.

The results indicate that the method is an effective tool for testing nonlinear circuits including bipolar junction transistors and junction field effect transistors.

The homotopy method is generalized and associated with a restart procedure and a numerical algorithm for solving differential equations. Testable sets of elements are found using the singular value decomposition. The procedure for selecting faulty elements, based on the minimal fault number rule, is developed. The method comprises both theoretical and practical aspects of fault diagnosis.

In SMT manufacturing, automation is the key to achieving the highest throughput at the lowest cost. Complex devices of various shapes and sizes often require final electrical adjustments under operating conditions to ensure conformance to electrical specifications. This paper describes the process of laser trimming completed SMT devices and the advantages it has over conventional trimming methods. The material presented is based on laser trimming systems currently used in SMT production applications that will also be described.