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In the new knowledge economy, intellectual property has become an important strategic issue. However, in many firms, the management of intellectual property (IP) is still divorced from business strategy. People still think that “managing IP strategically” means having an IP strategy rather than managing IP according to business strategy. We argue that intellectual property is strategic only to the extent that it links to the firm’s core capabilities and that not all intellectual property is core to business strategy. We present a model for identifying the function of intellectual property in a firm’s business strategy and present specific recommendations for protecting, valuing and generating IP from a strategic point of view.

Based upon the review of theoretical frameworks and the author's practical experiences in intellectual property (IP) management, the purpose of this paper is to propose a theoretical framework which intends to accord the current development of IP management and strategy in China. It is constituted of two engines, namely innovation engine and intellectual property engine which are related closely to management of technology – a strategic instrument in creating wealth and prosperity. The latter is also stated “5‐IPs” management pattern, i.e. intellectual property advantages, intellectual property economy, intellectual property strategy, intellectual property talents, and intellectual property culture as essential factors.

Briefly, elaborating basic concepts and main characteristics of “5‐IPs”, this work discusses the theoretical framework and the application of these pattern in Henan Province of PRC.

This work presents a whole picture of how the policy makers in Henan Province developed and implemented its IP management strategy. Theoretically, this work presents a strategic framework, which intends to create an innovation model and enables the decision‐makers and IP practitioners to make more appropriate arrangement when addressing IP related issues.

This study presents the crucial tenets of the strategic framework, which underpins the identification of the appropriateness and effectiveness of China's intellectual property right (IPR) strategy. The distinctiveness of the study lies in: advancing the current literature on the establishment of IPR system in China; presenting a case study of Henan Province in terms of how the province has developed its IP management strategy; and assessing the leading changes, impact and the policy implication after the implementation of the project.

This chapter summarizes the interdependence of network effects, compatibility standards and intellectual property rights (IPR) in the global economy. This interdependence is analyzed at the product market level and at the research and development level. The questions to be examined are: how IPR influence the provision of goods exhibiting network effects; the impact of network effects on the creation, dissemination and protection of intellectual property and of goods with strong intellectual property content; and strategic issues faced by firms and governments in goods that exhibit network effects. We answer these questions by studying how network effects influence the value of IPR and how in turn IPR may influence the size of networks. We highlight the central importance of IPR protection of interface standards for market outcomes, and how different types of IPR generate market power through interface standards. We review similarities of network effects in product markets and research networks as well as impediments to their expansion. We finally discuss alternative outcomes of standardization policies, institutional choices and strategic coordination efforts by firms. We emphasize how the answers to these questions are distinct in an international context.

A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.

A set of routers that are connected over communication channels can from network-on-chip (NoC). High performance, scalability, modularity and the ability to parallel the structure of the communications are some of its advantages. Because of the growing number of cores of NoC, their arrangement has got more valuable. The mapping action is done based on assigning different functional units to different nodes on the NoC, and the way it is done contains a significant effect on implementation and network power utilization. The NoC mapping issue is one of the NP-hard problems. Therefore, for achieving optimal or near-optimal answers, meta-heuristic algorithms are the perfect choices. The purpose of this paper is to design a novel procedure for mapping process cores for reducing communication delays and cost parameters. A multi-objective particle swarm optimization algorithm standing on crowding distance (MOPSO-CD) has been used for this purpose.

In the proposed approach, in which the two-dimensional mesh topology has been used as base construction, the mapping operation is divided into two stages as follows: allocating the tasks to suitable cores of intellectual property; and plotting the map of these cores in a specific tile on the platform of NoC.

The proposed method has dramatically improved the related problems and limitations of meta-heuristic algorithms. This algorithm performs better than the particle swarm optimization (PSO) and genetic algorithm in convergence to the Pareto, producing a proficiently divided collection of solving ways and the computational time. The results of the simulation also show that the delay parameter of the proposed method is 1.1 per cent better than the genetic algorithm and 0.5 per cent better than the PSO algorithm. Also, in the communication cost parameter, the proposed method has 2.7 per cent better action than a genetic algorithm and 0.16 per cent better action than the PSO algorithm.

As yet, the MOPSO-CD algorithm has not been used for solving the task mapping issue in the NoC.

Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique.

The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure.

The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%.

To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model.

The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications.

This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

The internationalisation of industries has spilled over to academia, whereby institutions of higher learning (IHL) increasingly compete in the graduate quality and applied graduate knowledge capabilities that they can offer. With increasing global competition for students, combined with the evolving need for lifelong learning in dynamic industries impacted by digital knowledge management, there is an opportunity for IHLs to be able to evolve to ensure their business models enable services and service delivery to cater to and help shape industry demands. This chapter will look at micro-credentialing (MC) and how the provision of MCs has changed along with the evolving IHL education environment. The demands of students, employers and ecosystem considerations will be addressed through a review of the current landscape, pathways to MC and how MC may be operationalised. The Bersteinian approach to pedagogic classification, which identifies the framework of knowledge as being communicable via three axes of singularism, regionalism and a wider generalist approach is referenced as a framework. The resultant recommendations that draw upon these foundations will conclude the chapter.

This article is a synthesis of consulting experience in managing the reality of the corporate university transition. It provides an objective context for this development and outlines the nature of the intellectual vacuum that exists between a company’s strategic learning needs and the provision available in the institutional intellectual supply chain. The emergent role of the corporate university in filling the gap is identified and a project management approach that facilitates and administratively enhances a highly networked corporate university development process is described.

We introduce a multi-level model of the dependence of interfirm network topologies on the distribution and commonality of information in a network and the information strategies pursued by its member firms. Network topology, information properties of the network, and firm-level action within the network form dynamic, recursive, cross-level relationships – information properties in the network determine firm-level action, which in turn impacts the network topology and information properties. We derive predictions about the kinds of information strategies that firms are likely to adopt and succeed with in different information regimes, and about the kinds and short- and long-run dynamics of network topologies expected under different information regimes. Our model sheds new light on network topologies as a dependent variable that can be explained by network-level information regimes and firm-level information strategies.

The purpose of this paper is to introduce and provide an insight into the benefits of outsourcing the procurement function for engineering commodity items.

Research into the literature presents the development of outsourcing procurement functions and this manuscript adds to the body of knowledge through introducing the outsourcing of engineering commodity procurement, illustrated with the case study example.

A US Aerospace Fortune 50 company has made savings by outsourcing the procurement of commodity engineering parts. This has occurred in two stages. Firstly the commodity procurement was locally outsourced and staff migrated to the service provider to whom commodity procurement was a core competence enabling them to offer cost savings. Secondly the back office and telephone service was moved to India, further reducing cost whilst enhancing the service through an increased headcount.

The paper provides the first example of the two stages of outsourcing engineering commodity procurement.