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Low-level logic fault testing ASIC simulation environment

1 School of Engineering and Physics, University of the South Pacific, Suva 19128, Fiji
2 Center for Information and Communication Technology, University of Trinidad and Tobago, Arima, Trinidad, West Indies
3 Department of Computer Science, College of Arts and Sciences, Troy University, Montgomery, AL 36103, USA
4 School of Information Technology and Engineering, Faculty of Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada
5 School of Engineering and Technology, Kaziranga University, Jorhat, Assam 785006, India

World Journal of Engineering

ISSN: 1708-5284

Article publication date: 22 July 2014



A low-level logic fault test simulation environment targeted towards application-specific integrated circuits (ASICs) in particular is proposed in this paper. The simulation environment emulates a typical built-in self-testing (BIST) environment with test pattern generator (TPG) that sends its outputs to a circuit (core) under test (CUT) and the output streams from the CUT are fed into an output response analyzer (ORA). The developed simulator is very suitable for testing embedded digital intellectual property (IP) cores-based systems. The paper describes the total test architecture environment, including the application of the logic fault simulator. Results on simulation on some specific International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 sequential benchmark circuits are provided as well for appraisal.



Assaf, M., Moore, L.-A., Das, S., Biswas, S. and Morton, S. (2014), "Low-level logic fault testing ASIC simulation environment", World Journal of Engineering, Vol. 11 No. 3, pp. 279-286.



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