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The purpose of this paper is to study the thermal warpage of a plastic ball grid array (PBGA) mounted on a printed circuit board (PCB) during the reflow process.

A thermal-mechanical coupling method that used finite-element method software (ANSYS 13.1) was performed. Meanwhile, a shadow moiré apparatus (TherMoiré PS200) combined with a heating platform was used for the experimental measurement of the warpage of PBGA according to the JEDEC Standard.

The authors found that the temperature profiles taken from the simulated results and experimental measurement are consistent with each other, only with a little and acceptable difference in the maximum temperatures. Furthermore, the maximum warpage measurements during the reflow process are 0.157 mm and 0.149 mm for simulation and experimental measurements, respectively, with a small 5.37 per cent difference. The experimental measurement and simulated results are well correlated. Based on the validated finite element model, two factors, namely, the thickness and dimension of PCB, are explored about their effect on the thermal warpage of PBGA mounted on PCB during the reflow process.

The paper provides a thorough parametrical study of the thermal warpage of PBGA mounted on PCB during the reflow process.

The findings in this paper illustrate methods of warpage study by combination of thermal-mechanical finite element simulation and experimental measurement, which can provide good guidelines of the PCB design in the perspective of thermal warpage during the reflow process.

This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.

This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.

Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.

The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.

This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.

The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.

The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

This paper aims to develop an estimation tool for warpage behavior of slim printed circuit board (PCB) array while soldering with electronic components by using finite element method. One of the essential requirements for handheld devices, such as smart phone, digital camera, and Note-PC, is the slim design to satisfy the customers’ desires. Accordingly, the printed circuit board (PCB) should be also thinner for a slim appearance, which would result in decreasing the PCB’s bending stiffness. This means that PCB deforms severely during the reflow (soldering) process where the peak temperature goes up to 250°C. Therefore, it is important to estimate PCB deformation at a high temperature for thermo-mechanical quality/reliability after reflow process.

A numerical simulation technique was devised and customized to accurately estimate the behavior of a thin printed board assembly (PBA) during reflow by considering all components, including PCB, microelectronic packages and solder interconnects.

By applying appropriate constraints and boundary conditions, it was found that PBA’s warpage can be accurately predicted during the reflow process. The results were also validated by warpage measurement, which showed a fairly good agreement with one and another.

For research limitations, there are many assumptions regarding numerical modeling. That is, the viscoplastic material property of solder ball is ignored, the reflow profile is simplified and the accurate heat capacity is not considered. Furthermore, the residual stress within the PCB, generated at PCB manufacturing process, is not included in this paper.

This paper shows how to calculate PBA warpage during the reflow process as accurately as possible. This methodology helps a PCB designer and surface-mount technology (SMT) process manager to predict a PBA warpage issue and modify PCB design before PCB real fabrication. Practically, this modeling and simulation process can be easily performed by using a graphical user interface (GUI) module, so that the engineer can handle an issue by inputting some numbers and clicking some buttons.

In a common sense manner, a numerical simulation method can decrease time and cost in manufacturing real samples. This PCB warpage method can also decrease product development duration and produce a new product earlier. Furthermore, PCB is a common component in all the electronic devices. So, this PCB warpage method can have various applications.

Because of an economic advantage, the development of a numerical simulation tool for estimating the thin PBA warpage behaviour during reflow process was attempted. The developed tool contains the features of detailed modeling for electronic components and contact boundary conditions of the supporting rails in the reflow oven.

This study aims to achieve customized prosthesis for total joint arthroplasty and total hip arthroplasty. Selective laser sintering (SLS) as additive manufacturing could enable small-scale fabrication of customized Ultra High Molecular Weight Polyethylene (UHMWPE) components; however, the processes for SLS of UHMWPE need to be improved.

This paper begins by improving the preheating system of the SLS fabricating equipment and then fabricating cuboids with the same size and cuboids with same volume and different size to study the warpage, demonstrating the effect of the value and uniformity of the preheating temperature on component fabrication. Warpage, density and tensile properties are investigated from the perspective of energy input density. Finally, complicated industrial parts are produced effectively by using optimized technological parameters.

The results show that components can be fabricated effectively after the optimization of the SLS technological parameters i.e. the preheating temperature the laser power the scanning interval and the scanning speed. The resulting warpage was found to be less than 0.1 mm along with the density as 83.25 and the tensile strength up to 14.1 Mpa. UHMWPE sample parts with good appearance and strength are obtained after ascertaining the effect of each factor on the fabrication of the sample parts.

It is very challenging to fabricate UHMWPE sample parts by SLS. This is a new step in the fabrication of customized UHMWPE sample parts.

The paper aims to deal with a tuning method to reduce warpage of microelectronic substrates.

There are three major processes involved in this method: calculating effective thermomechanical properties of substrates with simple regular electric artworks using 3D finite element (FE) analyses; fitting simplified expressions to the results from the FE analyses; and developing 2D FE models of substrates with arbitrarily complicated artwork using the simplified expressions. These three processes were used to estimate the warpage. An optimization procedure through iterative searches was used to obtain optimized trace widths and/or spacing in order to reduce the warpage.

Using a printed circuit board design to prove our concept, it was found that the warpage could be significantly reduced by modifying trace widths and/or spacing of the printed circuit board.

The paper focuses on a tuning method to reduce warpage of microelectronic substrates.

The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models.

The results obtained are encouraging and clearly show a considerable reduction in wafer deformation.

This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

Out‐of‐plane displacement (warpage) is one of the major thermomechanical reliability concerns for board‐level electronic packaging. The warpage and residual stresses can cause unreliability in the performance of electronic chip. An accurate estimation of the distortion and the residual stresses will help in selecting right combination of material for soldering and to determine the better assembly procedure of the chip. The purpose of this paper is to create a 3D nonlinear finite element model to predict the warpage, bending stresses, shear and peel stresses in a flip‐chip on board (FCOB).

A 3D finite element procedure has been developed considering the material nonlinearity during solidification for a FCOB assembly. Finite element results have been compared with the experimental values.

The present finite element method gives better approximation of residual warpage and stresses compared to analytical models available in the literature.

The 3D finite element approach considering the elasto‐plastic and temperature‐dependent material properties has not been attempted by any authors. Experiments have been conducted for the comparison of finite element values. The finite element results compare better than the methods available in the literature. Hence a better method for estimating the deformation and residual stresses in flip‐chip assembly has been suggested.

The purpose of this paper is to find the optimal values of process parameters in injection molding when both warpage and shrinkage are minimized.

In finding the optimal values, advantages of finite element software, Moldflow, and dual response surface method (dual RSM) combined with the nonlinear programming technique by Lingo are exploited. Considering the nine process parameters, injection time, injection pressure, packing pressure, packing time, cooling time, coolant temperature, mold‐open time, melting temperature and mold surface temperature, a series of mold analyses are performed to exploit the warpage and shrinkage data. In the analyses, warpage is considered the primary response, whereas shrinkage is the secondary response.

The results indicate that dual RSM combined with the nonlinear programming technique can outperform the Taguchi's optimization method. The optimal process values are also confirmed by re‐running experiments on Moldflow. Additionally, an auxiliary dual RSM model is proposed to search for a better result based on the given findings by dual RSM at the cost of running extra experiments. Based on dual RSM, a multiple objective optimization for the whole plastic product is finally suggested to integrate the dual RSM models that are developed for the individual nodes or edges.

This paper proposes a new method to find the optimal process for plastic injection molding.

In the electronic assembly industry, low-temperature soldering holds great potential to be used in surface mounting technology. Tin–bismuth (Sn–Bi) eutectic alloys are lead-free solders applied in consumer electronics because of their low melting point, high strength and low cost. This paper aims to investigate how to address the problem of hot tear crack formation during Sn–Bi low-temperature solder (LTS) in the mass production of consumer electronics.

This paper explored the development of hot tear cracks during Sn–Bi soldering in the fabrication of flip chip ball grid arrays. Experiments were designed to simulate various conditions encountered in Sn–Bi soldering. Quantitative analysis was conducted on the number of hot tear cracks observed in different alloy compositions and solder volumes to explore the primary cause of hot tear cracks and possible methods to suppress crack formation.

Hot tear cracks existed in Sn–Bi solders with different bismuth (Bi) contents, but increasing the solder volume reduced the number of hot tear cracks. Experiments were designed to test the degree of chip transient thermal warpage with temperature change, and, according to the results, glue was dispensed in specific areas to reduce chip warpage deformation. Finally, the results of combined process experiments pointed to an effective method of low-temperature soldering to suppress hot tear cracks.

The study focuses on Sn–Bi solders only without other solder pastes such as SAC305 or Sn–Zn series.

With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles electronics, solar photovoltaic and other field, there will be more and more demand for low- temperature, energy-saving, lead-free solders. Therefore, this study will help the industry to roll out LTS (Sn–Bi) solutions rapidly.

In the long term, lean and green manufacturing is expected to be essential for maintaining an advanced manufacturing industry across the world. Developing new LTSs and soldering processes is the most effective, direct solution for energy conservation and emission mitigation. With the growing popularity of smart electronics, especially in intelligent terminals, new energy vehicles and solar photovoltaics, there would be an increased demand for low-temperature, energy-saving, lead-free techniques.

Although there are many methods that can be used to suppress hot tear cracks, there is little research on how to control the hot tear cracks caused by the low-temperature soldering of Sn–Bi in laptop applications. The authors studied the hot tear cracks that developed during the world’s first mass production of 50 million personal laptops based on low-temperature Sn–Bi alloy solder pastes. By controlling the Bi content, redesigning the solder paste printing process (e.g. through a printer’s stencil) and adding dispensing processes, the authors obtained reliable and stable experimental data and conclusions.

The purpose of this paper is to propose a new surface model combining the eccentric shell with multi-point constraint (MPC) for warpage prediction of injection molded plastics.

In this paper, three benchmark tests and a practical example are implemented to evaluate the performance of the new surface model and existing models.

The results demonstrate that the proposed model could give satisfactory solutions and has advantages over the existing models.

More precisely predicted warpage field for injection molded plastics can be achieved with the purposed model, such as that in the practical case.

The surface models are efficient and still popular for practical injection molding analysis. However, the existing models for warpage prediction cannot properly represent the true strain energy and obey material continuity assumption, and also they have not been assessed rigorously by benchmark tests. To overcome above-mentioned difficulty, a new surface model is proposed, which employs the eccentric shell without shear factor and MPC equation that ensuring material continuity. The results from experiment illustrate that the new model is superior to existing models.