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A high percentage of circuit boards manufactured in the electronics industry are of an irregular shape and are produced on a standard panel outline to facilitate assembly handling. The unused pieces of circuit board pass through the same processes as the useful parts and are normally discarded. This excess material could, among other things, be used to evaluate the quality of a bare board or an assembly. This paper will highlight the usefulness of designing test patterns on this excess material, namely test coupons, in terms of how these can be used to monitor all of the manufacturing and assembly process steps. It will also show how these coupons can be used to make the board easier to assemble and how they may actually lead to an improvement in the quality of the assembly and an increase in production yields. Suggestions will be made as to the types of test pattern that can be used, as well as how these patterns can be utilised as process control checkers. Since the test coupons are incorporated in the board design, a quality check of 100% of the boards that are being processed is possible. This would highlight any board‐to‐board variation if it were present. It would also allow for destructive testing to be carried out, without damaging any of the working product. The applications of these patterns are wide ranging. They can be used to check bare board quality—etch definition, layer registration, plating quality, solder mask definition etc. They can also be used to monitor the assembly processes for SMT and conventional PTH assembly types—cut and clinch quality, paste printing quality, onsertion accuracy, reflow/flow soldering quality and assembly cleanliness, among others. Many of these applications are examined in this paper.

The High Density Packaging Users Group conducted a substantial study of the solder joint reliability of high‐density packages using lead‐free solder. The design, material, and assembly process aspects of the project are addressed in this paper. The components studied include many surface mount technology package types, various lead, and printed circuit board finishes and paste‐in‐hole assembly.

Encapsulant materials for flip‐chip‐on‐board (FCOB) were developed to address issues that have been observed during assembly of consumer electronic products on a high volume manufacturing FCOB/SMT line. The viscosity, surface tension, and filler particle sizes of several encapsulants were studied in an attempt to correlate these properties to their recorded underfill times and to observe their flow properties under the gap. Materials characterization studies were performed to determine their glass transition temperatures (Tg), tensile elastic and loss moduli (E′ and E′′), coefficients of thermal expansion (CTE), and apparent strengths of adhesion (ASA). In addition, reliability tests were conducted, and several promising materials were identified. The ASA of the encapsulant to the die passivation and the printed circuit board (PCB) is critical to the robustness of the assembly. Studies were conducted to observe the ASA as a function of FCOB assembly conditioning prior to underfilling and the degradation of the ASA as a function of humidity exposure. The ASA of the FCOB encapsulants was highest when the assembly was “baked‐out” prior to underfilling. Conditioning the assemblies for 24 hours at 23°C/85 per cent RH, to simulate the “worse case” factory environment, reduced the ASA. The ASA was also reduced when the “baked‐out” assemblies were placed in the 85°C/85 per cent RH chamber after underfilling. Although the ASA was decreased when the boards were not “baked‐out”, the reliability performance was not affected during air to air temperature cycling (AATC). A new class of low stress encapsulant materials systems were developed to reduce the stress state of the backside of the die. Studies showed that for specific materials compositions, the stress was proportional to the glass transition temperature of the encapsulant. In addition, it was observed that the stress state was a function of humidity, temperature, and time. FCOB assemblies were built with several low stress encapsulants and placed in reliability testing and they performed as well as assemblies underfilled with the qualified encapsulant.

This paper is an examination of residues on printed wiring boards and printed wiring assemblies. Sources of residues are illustrated and the effects of various residues are discussed. Case studies are presented for bare board cleanliness issues, water soluble flux and aqueous cleaning processes, and low solids flux (no‐clean) processes, with and without cleaning. The case studies reflect lessons learned in various process troubleshooting efforts. Residues in this paper were characterized using advanced ion chromatography procedures. In addition, some data on surface insulation resistance (SIR) are presented.

Most setup management techniques associated with electronic assembly operations focus on component similarity in grouping boards for batch processing. These process planning techniques often minimize setup times. On the contrary, grouping with respect to component geometry and frequency has been proved to further minimize assembly time. Thus, we propose the Placement Location Metric (PLM) algorithm to recognize and measure the similarity between printed circuit board (PCB) patterns. Grouping PCBs based on the geometric and frequency patterns of components in boards will form clusters of locations and, if these clusters are common between boards, similarity among layouts can be recognized. Hence, placement time will decrease if boards are grouped together with respect to the geometric similarity because the machine head will travel less. Given these notions, this study develops a new technique to group PCBs based on the essences of both component commonality and the PLM. The proposed pattern recognition method in conjunction with the Improved Group Setup (IGS) technique can be viewed as an extended enhancement to the existing Group Setup (GS) technique, which groups PCBs solely according to component similarity. Our analysis indicates that the IGS performs relatively well with respect to an array of existing setup management strategies. Experimental results also show that the IGS produces a better makespan than its counterparts over a low range of machine changeover times. These results are especially important to operations that need to manufacture quickly batches of relatively standardized products in moderate to larger volumes or in flexible cell environments. Moreover, the study provides justification to adopt different group management paradigms by electronic suppliers under a variety of processing conditions.

The transition to complex printed board assemblies in modern high technology equipment is described. These low voltage, densely packed PBAs with their decreasing insulation paths, manufactured for greatest speed with highly activated solder fluxes, demand both awareness and action to achieve the degree of cleanliness compatible with reliability requirements. This paper sets forth activities under way in Australia to define and adopt cleanliness Standards for use throughout the nation's manufacturing industry. It identifies and defines cleanliness and methods used to achieve and measure contamination that is introduced during PBA manufacture.

For over 30 years, wave soldering has been the most popular and most economical method for mass soldering of electronic assemblies. For conventional circuits, this is a mature technology. Training, proper board design, process control during board fabrication, assembly and soldering and, finally, an awareness of the need for solderability have resulted in very high manufacturing yields in some companies with the associated high quality and much improved profits which result by doing it right the first time. With the introduction of surface mount technology, the same concerns need to be addressed. However, due to the smaller size of components and higher densities, new problems arise. This paper presents some of the concerns encountered in wave soldering of surface mount assemblies.

Presents an integrated approach to assembly planning for manufacturing printed circuit boards (PCBs). The integrated manufacturing assembly planning system (IMAPS) is a system that incorporates knowledge‐based techniques to assist process engineers with the development of assembly plans for building PCBs. IMAPS has been developed in a two‐year project with a multinational telecommunications manufacturer and the Alberta Research Council of Canada. The scope of IMAPS is to develop an integrated environment that takes full advantage of electronic information for assembly planning of PCBs. Several functions in the company can be integrated with IMAPS, including product design, detailed assembly planning, line balancing and generation of shop floor drawings. Information stored in the manufacturing and design databases of the corporation, about a PCB to be assembled, is employed by a knowledge‐based module to generate assembly plans to build the PCB. A line balancing procedure is employed to select the most adequate assembly plan of those generated by the knowledge‐based module. The final assembly plan is then presented to the operators as a diagram with instructions for the assembly of the PCB. IMAPS has increased the speed to generate assembly plans from 120 hours to four hours. The final computer‐aided assembly planning system implemented in the company has taken the concepts developed in IMAPS; they have been implemented in C and C++. Lessons and experiences learned while developing and implementing IMAPS are presented.

Assembly planning and scheduling are two major functions in circuit board manufacturing. Currently, assembly plans are developed in the absence of information about the state of the shop floor at the execution time of the assembly operation. In effect, these assembly plans may impose unnecessary restrictions on scheduling. As a result, scheduling conflicts, bottlenecks, imbalance in assembly lines and machine congestion that lead to lateness and excessive production and shipping costs are inevitable. Compares the performances of the traditional method of isolated planning and scheduling with a proposed method of simultaneous generation of assembly plans and schedules in electronic assembly operations. Simulated scenarios indicate the potential superiority of the integrated system.

Notes that, until now, to route robotics travel, most investigations have utilized the fixed coordinate of placement points and magazine of the traveling salesman problem (TSP) method to sequence the placement points after the magazine has been arbitrarily assigned. Points out that, in fact, robotics travel routing should be based on a relative coordinate because the robotics, board and magazine simultaneously move at different speeds during assembly. Consequently, the coordinates of placement point and magazine are constantly changing. In this study, a novel tabu search (TS) based approach is presented. The proposed approach can arrange the placement sequence and assign the magazine slots to yield a performance better than the conventional one. Results presented herein also demonstrate that the larger the number of placement points and/or part numbers, the better the performance.