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In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five‐point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

The coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB) materials causes a reliability issue for ball grid array type electronic packages. This makes it difficult for conventional wafer level chip scaled packaging (WLCSP) with large die to satisfy the reliability requirements. Therefore, in this study a novel solder joint protection‐WLCSP (SJP‐WLCSP) structure is proposed to overcome the reliability issue.

The SJP‐WLCSP makes use of a delaminating layer to reduce the problem of CTE mismatch. In the SJP‐WLCSP, a delaminating layer is interposed between the top layer of the chip and the bottom insulating layer of the redistribution copper metal traces. As a result, the stress on the solder joints can be released by allowing cracks to form in the delaminating layer.

To elucidate the thermo‐mechanical behaviour of tin‐lead eutectic solder joints and copper traces, a non‐linear analysis, based on a 3D finite element (FE) model, under accelerated thermal test loadings was carried out. The maximum equivalent stress/strain in the solder joints predicted by the FE simulation were found to diminish significantly when applying the delaminating layer. In addition, parametric FE analysis was also applied in this study, and based on the design concepts within this study, a robust novel SJP‐WLCSP could be achieved.

In this work, a new packaging concept with high reliability, low cost and easy fabrication was developed to reduce the shear stress in the solder joints due to the CTE mismatch between silicon chips and organic PCBs.

The study investigates the sub process behaviour in stencil printing of type‐6 and type‐7 particle size distribution (PSD) Pb‐free solder pastes to assess their printing limits.

Two solder pastes were used in a design of experiments approach to find optimal printing parameters

Solder paste printing has been achieved to ultimately produce 30 μm deposits at 60 μm pitch for full area array patterns using a type‐7 Pb‐free solder paste. For a type‐6 PSD solder paste, full area array printing was limited to 50 μm deposits at 110 μm pitch. However, for peripheral printing patterns, 50 μm deposits at 90 μm pitch were obtained. The disparities in the behaviour of the two paste types at different geometries can be attributed to differences in the sub‐processes of the stencil printing. The paste release of the type‐6 paste from the stencil apertures at fine pitch was superior to the type‐7 paste, which may be attributed to the finer particle paste producing an increased drag force along the stencil aperture walls. However, the type‐7 paste was able to fill the smallest aperture openings, ultimately to 30 μm, thus producing full array printing patterns at uniquely small pitches.

This advancement in the stencil printing process has been made possible by refinements to both solder paste design and stencil manufacturing technology. Adjustments in the solder paste rheology have enabled successful printing at ultra fine pitch geometries. This, together with selecting appropriate printing parameters such as printing speed, pressure, print gap and separation speed, allows a practical printing process window. Moreover, advancements in stencil fabrication methods have produced “state‐of‐the‐art” stencils exhibiting very precisely defined aperture shapes, with smooth walls at very fine pitch, thus allowing for improved solder paste release at very small dimensions.

The results can be used to present a low cost solution for Pb‐free flip chip wafer bumping. Furthermore, the results indicate that type‐6 and type‐7 solder pastes should be applied to/selected for specific application geometries.

Presents an overview of memory chip yield enhancement techniques by injection of fault tolerance. As memory chips are more prone to defects, the yield of good chips from a silicon wafer governs their production cost. As shown, most fault tolerance techniques assume a relatively large area overhead which results in additional costs in terms of the silicon used as well as the lower number of chips/wafers produced. Proper management of fault tolerance, as by the word redundancy approach, adds an almost negligible area overhead to the chip and leads to considerably higher yields.

A package performance bottleneck is developing because of the inability to densely wire single chip modules together on the printed wiring board. An array processor, constructed by means of various high performance packaging techniques, demonstrates that multichip modules of even modest size can give dramatic improvements in the packaging figure of merit.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

A new high precision reflow soldering/bonding machine, the Farco F‐130, ideal for automatically placing and accurately soldering surface mount devices such as flatpacks, chip carriers, SO and VSO components is available from Dage. TAB (Tape Automated Bonding) components can also be processed using the F‐130's modular system design which allows the machine to be more versatile in application.

Whatever one may feel is the importance of particular interconnection and assembly technologies with which one is associated, Thin Film or Thick Film Hybrid, PCB Through Hole, Surface Mounting, etc., the driving force in electronics is the high degree of low cost functionality brought by semiconductor technology. However, semiconductor science cannot provide systems solutions on its own and needs to be combined with suitable interconnection and assembly technologies to bring its potential processing power to fulfilment. Hybrid technology holds a key role in the use of silicon in overall system integration. On hybrid substrates semiconductors can be applied in any of the forms available, from bare dice to encapsulated, tested and burnt‐in complex functions in LSI. Over the years hybrids have developed, needing semiconductors as the active elements in providing functional modules. The relationship between the technologies has been close but not always in perfect harmony at the commercial interfaces. The first part of this paper reviews development of semiconductors in relation to the forms of packaging available for application in hybrid assembly including the emergent means being adopted to tackle the problems of ever increasing lead counts that will be with us for some time until the dream of total self‐sufficiency on silicon becomes a reality. The second part of the paper reviews silicon design options with the emphasis on the relevance of combining silicon implementation with hybrid methods.