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This study aims to investigate the several parameters in wafer-level packaging (WLP) to find the most critical factor impacting the thermal fatigue life, such as the height of copper post, the height of solder bump, the thickness of chip. The FEA results indicate the height of solder bumps is the most important factor in the whole structure.

The copper post bumps with 65 µm pitch are proposed to investigate the thermal-mechanical performance of WLP. The thermal cycle simulation is used to evaluate the reliability of WLP by using finite element analysis (FEA). Taguchi method is adopted to obtain the sensitivity of parameters of three-dimension finite element model, for an optimized configuration.

It can be found that the optimal design has increased thermal fatigue life by 147% compared with the original one.

It is concluded that the finite element simulation results show outstanding thermal-mechanical performances of the proposed 65 µm pitch copper post bumps of WLP, including low plastic strain, high thermal fatigue life, which are desired for mobile device.

The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).

In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.

It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.

In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss.

An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples.

The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth.

The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions.

To provide an insight and view of the expected directions for microelectronic packaging, at chip level, that ties in current developments to the needs envisaged by emerging technology roadmaps.

The requirements for packaging semiconductor devices have become a new technology driver for the electronics “Final Manufacturing” industry. In line with forecasts and roadmaps, the expected multitude of options are being developed in order to meet the demand of an industry which requires ever more complex devices which exhibit both higher reliability and lower cost.

As application potentials develop, so package cost becomes the driver. In turn, low cost package solutions are becoming the drivers for new technologies such as “last‐mile” fibre optic Telecom systems, 3G phones, bluetooth and sensors. MEMS devices are a key example of how applications are pushing the technologies to create cost effective packaging.

The emerging packaging technologies, currently BGA's and chip size packaging's (CSP), continue to develop to meet the needs of electronic devices, driven by the “smaller, faster, cheaper” paradigm. However the final manufacturing and testing aspects of such needs are often overlooked and as such the test industry faces a number of severe challenges in terms of handling these new package technologies.

By looking at the market trends and how these new technologies are developing, especially with respect to emerging developments in CSP, flip chip and wafer level packaging, solutions for many of the challenges posed can be determined.

This paper provides a market analysis of the trends and directions of the chip packaging industry. It has taken data from a wide number of sources of market information and compared the expectations of each to actual emerging applications. The resulting information is expected to become a benchmark for this aspect of the semiconductor manufacturing industry.

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five‐point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

The purpose of this paper is to demonstrate a novel 3D system-in-package (SiP) approach. This new packaging approach is based on stacked silicon submount technology. As demonstrators, a smart lighting module and a sensor systems were successfully developed by using the fabrication and assembly process described in this paper.

The stacked module consists of multiple layers of silicon submounts which can be designed and fabricated in parallel. The 3D stacking design offers higher silicon efficiency and miniaturized package form factor. This platform consists of silicon submount design and fabrication, module packaging, system assembling and testing and analyzing.

In this paper, a smart light emitting diode system and sensor system will be described based on stacked silicon submount and 3D SiP technology. The integrated smart lighting module meets the optical requirements of general lighting applications. The developed SiP design is also implemented into the miniaturization of particular matter sensors and gas sensor detection system.

SiP has great potential of integrating multiple components into a single compact package, which has potential implementation in intelligent applications.