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Reliability analysis of a novel fan‐out type WLP

Ming‐Chih Yew (Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Republic of China)
Mars Tsai (Advanced Chip Engineering Technology, Inc., Hu‐Kou, Taiwan, Republic of China)
Dyi‐Chung Hu (Advanced Chip Engineering Technology, Inc., Hu‐Kou, Taiwan, Republic of China)
Wen‐Kun Yang (Advanced Chip Engineering Technology, Inc., Hu‐Kou, Taiwan, Republic of China)
Kuo‐Ning Chiang (Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Republic of China)

Soldering & Surface Mount Technology

ISSN: 0954-0911

Article publication date: 26 June 2009

809

Abstract

Purpose

The wafer level package (WLP) is a cost‐effective solution for electronic packaging and has been increasingly applied in recent years. The purpose of this paper is to propose a newly developed packaging technology, based on the concepts of the WLP, the panel base package (PBP) technology, in order to further obtain the capability of signal fan‐out for fine‐pitched integrated circuits (ICc).

Design/methodology/approach

In the PBP, the filler material is selected to fill the trench around the chip and provide a smooth surface for the redistribution lines. Therefore, the solder bumps could be located on both the filler and the chip surface and the pitch of the chip side is fanned‐out. The design concept and the manufacturing process of the PBP would first be described in this study. The three‐dimensional finite element model is established based on the real testing sample and the thermo‐mechanical behavior of the PBP is simulated.

Findings

It is found that the solder joint reliability of the PBP can be highly improved because of the applied stress buffer layer. However, the accumulated stress/strain from the coefficient of thermal expansion mismatch may transfer to the metal lines in package. In order to enhance the robustness of the redistribution lines, the bypassed type interconnect is suggested. Moreover, the trace/pad connecting junction and the conductive via which have smooth outline are preferred to avoid stress concentration effects.

Originality/value

In this paper, a low‐cost and short time‐to‐market packaging technology is proposed which is especially suitable for high density IC devices. The PBP technology has the ability to meet the requirements of major reliability testing conditions and it will have a high potential for application in the near future.

Keywords

Citation

Yew, M., Tsai, M., Hu, D., Yang, W. and Chiang, K. (2009), "Reliability analysis of a novel fan‐out type WLP", Soldering & Surface Mount Technology, Vol. 21 No. 3, pp. 30-38. https://doi.org/10.1108/09540910910970394

Publisher

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Emerald Group Publishing Limited

Copyright © 2009, Emerald Group Publishing Limited

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