To read this content please select one of the options below:

Wafer level packaging of compliant, chip size ICs

Joseph Fjelstad (Pacific Consultants, Mountain View, California, USA)
Thomas DiStefano (Decision Track, Mountain View, California, USA)
Anthony Faraci (Independent consultant in Georgetown, Texas, USA)

Microelectronics International

ISSN: 1356-5362

Article publication date: 1 August 2000



The concept of packaging integrated circuits while they are still in wafer form has captured the imagination of semiconductor manufacturers and packagers around the globe. One such concept, referred to as wide area vertical expansion (WAVETM) technology promises to provide a relatively easy method for cost effectively interconnecting ICs while still on the wafer. Moreover the fundamental technology is amenable to the production of “virtual wafers” where individual IC chips can be assembled en masse. The virtual wafer variation also allows for die shrink to occur, while the IC package footprint remains constant. The technology is based on concepts that allow for the mass assembly and production of compliant packages both directly on the wafer and in “virtual wafer” format where individual chips are bonded directly to the flexible pellicle. This paper examines this important new packaging technology concept in terms of the process and device and the implications and future directions the technology is likely to take.



Fjelstad, J., DiStefano, T. and Faraci, A. (2000), "Wafer level packaging of compliant, chip size ICs", Microelectronics International, Vol. 17 No. 2, pp. 23-27.




Copyright © 2000, MCB UP Limited

Related articles