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The purpose of this paper was to investigate how variations in the geometry of silicon chips and the presence of surface defects affect their static bending properties. By comparing the bending radius and strength across differently sized and treated chips, the study sought to understand the underlying mechanics that contribute to the flexibility of silicon-based electronic devices. This understanding is crucial for the development of advanced, robust and adaptable electronic systems that can withstand the rigors of manufacturing and everyday use.

This study explores the impact of silicon chip geometry and surface defects on flexibility through a multifaceted experimental approach. The methodology included preparing silicon chips of three distinct dimensions and subjecting them to thinning processes to achieve a uniform thickness verified via scanning electron microscopy (SEM). Finite element method (FEM) simulations and a series of four-point bending tests were used to analyze the bending flexibility theoretically and experimentally. The approach was comprehensive, examining both the intrinsic geometric factors and the extrinsic influence of surface defects induced by manufacturing processes.

The findings revealed a significant deviation between the theoretical predictions from FEM simulations and the experimental outcomes from the four-point bending tests. Rectangular-shaped chips demonstrated superior flexibility, with smaller dimensions leading to an increased bending strength. Surface defects, identified as critical factors affecting flexibility, were analyzed through SEM and atomic force microscopy, showing that etching processes could reduce defect density and enhance flexibility. Notably, the study concluded that surface defects have a more pronounced impact on silicon chip flexibility than geometric factors, challenging initial assumptions and highlighting the need for defect minimization in chip manufacturing.

This research contributes valuable insights into the design and fabrication of flexible electronic devices, emphasizing the significant role of surface defects over geometric considerations in determining silicon chip flexibility. The originality of the work lies in its holistic approach to dissecting the factors influencing silicon chip flexibility, combining theoretical simulations with practical bending tests and surface defect analysis. The findings underscore the importance of optimizing manufacturing processes to reduce surface defects, thereby paving the way for the creation of more durable and flexible electronic devices for future technologies.

Briefly reviews previous literature by the author before presenting an original 12 step system integration protocol designed to ensure the success of companies or countries in their efforts to develop and market new products. Looks at the issues from different strategic levels such as corporate, international, military and economic. Presents 31 case studies, including the success of Japan in microchips to the failure of Xerox to sell its invention of the Alto personal computer 3 years before Apple: from the success in DNA and Superconductor research to the success of Sunbeam in inventing and marketing food processors: and from the daring invention and production of atomic energy for survival to the successes of sewing machine inventor Howe in co‐operating on patents to compete in markets. Includes 306 questions and answers in order to qualify concepts introduced.

Selection of the correct interconnection technique for high lead count integrated circuits is dependent on technical and economic factors, in particular in small batch production of application specific devices (ASICs). This paper reviews some of the interconnection options and describes work where some advances in high density interconnection have been made.

A major limitation to achieving significant speed increases in VLSI lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of fifth generation supercomputing, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information between chips or between boards. As the on‐chip performance of VLSI continues to improve via the scale‐down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realised in reducing cross‐talk between the metallic routings, and the interconnects need no longer be constrained to the plane of the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

The International Electronic Components Show in Paris in November, 1983, provided the occasion for a very successful meeting of ISHM‐France which attracted 170 attendees. The following presentations were given:

This paper's purpose is to review the design of a flip chip thermal test vehicle.

Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn‐in simulation are outlined and the design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. The design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also explained.

Describes the design considerations and processes of the package substrate and printed‐circuit board with special emphasis on the physical routing of the thermal test chip structures. These design processes are supported with thermal data from various finite‐element analyses carried out to evaluate the capability and limitations of thermal test vehicle design.

The validation and calibration procedures of a thermal test vehicle are presented in this paper.

The purpose of this paper is to discuss the fabrication technology and test of thermo-pneumatic actuator utilizing Si₃N₄-polyimide thin film membrane. Thin film polyimide membrane capped with Si₃N₄ thin layer is used as actuator membrane which is able to deform through thermal forces inside an isolated chamber. The fabricated membrane will be suitable for thermo-pneumatic-based membrane actuation for lab-on-chip application.

The actuator device consisting of a micro-heater, a Si-based micro-chamber and a heat-sensitive square-shaped membrane is fabricated using surface and bulk-micromachining process, with an additional adhesive bonding process. The polyimide membrane is capped with a thin silicon nitride layer that is fabricated by using etch stop technique and spin coating.

The deformation property of the membrane depend on the volumetric expansion of air particles in the heat chamber as a result of temperature increase generated from the micro-heater inside the chamber. Preliminary testing showed that the fabricated micro-heater has the capability to generate heat in the chamber with a temperature increase of 18.8 °C/min. Analysis on membrane deflection against temperature increase showed that heat-sensitive thin polyimide membrane can perform the deflection up to 65 μm for a temperature increase of 57°C.

The dual layer polyimide capped with Si₃N₄ was used as the membrane material. The nitride layer allowed the polyimide membrane for working at extreme heat condition. The process technique is simple implementing standard micro-electro-mechanical systems process.

Bumping is a prerequisite for flip‐chip attachment of bare dies. For silicon semiconductors bumping is normally performed on the ICs at wafer scale. Bumping can be performed by micro‐plating or vacuum deposition techniques. Mechanical methods are also well known. In this paper a bumping process based on tin/lead alloy plating is reported. The plating bath presented enables the deposition of both solder compositions used for flip‐chip attachment, the eutectic and the lead‐rich. All key issues of the plating process covering plating equipment, electrolyte characteristics and plating process parameters are discussed. Methods of bump characterisation and quality assurance are reported as an important part of the bumping process. The deciding process parameters leading to high quality solder bumps are demonstrated.

The purpose of this paper is to investigate the durability of radio‐frequency identification (RFID) chips assembled on flexible substrates (paper and foil), with materials evaluated with regard to mechanical stresses and dependence on the applied substrate, antenna materials, chip pad printing and chip encapsulation.

RFID chips were assembled to antennas screen printed on flexible substrates. Shear and bending tests were conducted in order to evaluate the mechanical durability of the chip joints depending on the materials used for mounting the RFID chip structures. X‐ray inspection and cross sectioning were performed to verify the quality of the assembly process. The microstructure and the resistance of the materials used for chip pads were investigated with the aim of determining the conductivity mechanism in the printed layers.

Addition of carbon nanotubes to the conductive adhesive (CA) provided a higher shear force for the assembled RFID chips, compared to the unmodified conductive adhesive or a polymer paste with silver flakes. However, this additive resulted in an increase in the material's resistance. It was found that the RFID substrate material had a significant influence on the shear force of mounted chips, contrary to the materials used for printing antennas. The lower shear force for chips assembled on antennas printed on paper rather than on foil was probably connected with its higher absorption of solvent from the pastes. Increasing the curing temperature and time resulted in an additional increase in the shear force for chips assembled to antennas printed on foil. A reverse dependence was observed for chips mounted on the antennas made on paper. An improvement in the durability of the RFID chip structures was achieved by chip encapsulation. Bending tests showed that a low‐melting adhesive was the best candidate for encapsulation, as it provided flexibility of the assembled structure.

Further studies are necessary to investigate the mechanical durability of RFID chips assembled with a conductive adhesive, with different addition levels and types of carbon nanotubes.

The results revealed that the best candidate for providing the highest RFID chip durability related to mechanical stresses was the low‐melting adhesive. It can be recommended for practical use, as it simplified the assembly process and reduced the curing step in the encapsulation of the RFID devices. From the results of shear testing, conductive adhesives with carbon nanotubes can be used in RFID chip assembly because of their ability to increase the shear force of joints created between the antenna and the chip.

In this paper, the influence of the materials used for antenna, chip pads, encapsulation and the curing conditions on the mechanical durability (shear and bending) of RFID chips was analyzed. Commercial and elaborated materials were compared. Some new materials containing a conductive adhesive and carbon nanotubes were proposed and tested in RFID chip assembly to antennas printed on flexible substrates (paper and foil).

Information technology (IT) systems are already ubiquitous, and their future growth is expected to drive the global economy for the next several decades. However, energy consumption by these systems is growing rapidly, and their sustained growth requires curbing the energy consumption, and the associated heat removal requirements. Currently, 20-50 percent of the incoming electrical power is used to meet the cooling demands of IT facilities. Careful co-optimization of electrical power and thermal management is essential for reducing energy consumption requirements of IT equipment. Such modeling based co-optimization is complicated by the presence of several decades of spatial and temporal scales. The purpose of this paper is to review recent approaches for handling these challenges.

In this paper, the authors illustrate the challenges and possible modeling approaches by considering three examples. The multi-scale modeling of chip level transient heating using a combination of Progressive Zoom-in, and proper orthogonal decomposition (POD) is an effective approach for chip level electrical/thermal co-design for mitigation of reliability concerns, such as Joule heating driven electromigration. In the second example, the authors will illustrate the optimal microfluidic thermal management of hot spots, and large background heat fluxes associated with future high-performance microprocessors. In the third example, data center facility level energy usage reduction through a transient measurements based POD modeling framework will be illustrated.

Through modeling based electrical/thermal co-design, dramatic savings in energy usage for cooling are possible.

The multi-scale nature of the thermal modeling of IT systems is an important challenge. This paper reviews some of the approaches employed to meet this challenge.