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The IBM ceramic quad flat pack (CQFP) is a high performance, low‐cost chip carrier for surface mount assembly. It is an extension of metallised ceramic (MC) and metallised ceramic with polyimide (MCP) product technologies. These finished modules conform to JEDEC I/O and footprint standards. They are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead pitches. Connection from integrated circuit (IC) to carrier is performed using flip‐chip (C4 ‐ Controlled Collapse Chip Connection) attach. Silicon die size and the quantity of C4 connections for flip‐chip joining have historically been constrained to reduce early life failures caused by solder fatigue wearout. This DNP (distance from neutral point of chip footprint) limitation has been overcome with increasing usage of epoxy encapsulation as a flip‐chip underfill. The encapsulant matches the coefficient of thermal expansion (CTE) of C4 solder and minimises stresses on the interconnection. This enhancement provides a substantial reliability improvement in comparison with unencapsulated packages. Also, it enables larger die with smaller C4 solder bumps on finer pitches to be assembled on ceramic carriers. Recent product development and testing have extended flip‐chip on ceramic packaging technology even further than previously anticipated. Test die up to 20 mm in size with over 2,000 C4 joints have been successfully assembled, encapsulated, stress tested and qualified in CQEP modules. Flip‐chip assembly and encapsulation of C4 connections on very large die to CQFP components have been implemented into IBM manufacturing production. This large‐scale packaging enhancement continues to demonstrate that flip‐chip underfill eliminates the intrinsic failure mechanisms associated with fatigue wearout. This provides a significant technology extension to this low‐cost and high reliability product offering.

Polymer thick film (PTF) technology provides the lowest cost, cleanest and most efficient manufacturing method for producing flexible circuits. Non‐contact radio frequency (RF) smart cards and related information transaction devices, such as RFID tags, appear to be a good fit for PTF‐flex. Flip chip also seems well suited for these “contactless” RF transceiver products. Flip chip and PTF adhesive technologies are highly compatible and synergistic. All PTF SMT adhesives assembly methods are viable for flip chip. However, the merging of flip chip with PTF‐flex presents major challenges in design, materials and processing. This paper will compare assembly methods and discuss obstacles and solutions for state‐of‐the‐art flip chip on flex within the RFID product environment.

3D chip stacking is a key technology for 3D integration in which two or more chips are stacked with vertical interconnections. In the case of multi chip stacking with fine pitch microbump connections, capillary dispensing presents big limitations in terms of cost and processability. The purpose of this paper is to describe the way in which wafer‐level underfill (WLUF) process development was carried out with particular emphasis on microbump height coplanarity, bonding pressure distribution and the alignment of the microbumps. A three factorial design of experiment (DOE) was also conducted to enhance the understanding of the factors impacting the WLUF process such as bonding pressure, temperature and time on reliability test.

B‐staged WLUF was laminated on an 8″ wafer with a 30 μm pitch bump structure of 8 μm Cu/5 μm Sn2.5Ag Pb‐free solder. After wafer dicing, the chip with the WLUF was assembled on a substrate chip with the same bump structure using a high accuracy bonder. The substrate chip had metalisation (wiring) to enable evaluation of the electrical characteristics of the bonded daisy chain chips as they varied with material bonding process conditions and reliability testing.

The WLUF bonding process development pertaining to the processability and reliability for the flip chip assembly using Cu/SnAg microbumps was successful in this work.

The development of a WLUF bonding process that offers reliability for flip chip assembly using Cu/SnAg microbumps has been presented in this work. The critical steps, such as alignment of the WLUF coated chip with the substrate chip and void elimination, which enable this technology to work were optimised.

The purpose of this paper is to investigate the durability of radio‐frequency identification (RFID) chips assembled on flexible substrates (paper and foil), with materials evaluated with regard to mechanical stresses and dependence on the applied substrate, antenna materials, chip pad printing and chip encapsulation.

RFID chips were assembled to antennas screen printed on flexible substrates. Shear and bending tests were conducted in order to evaluate the mechanical durability of the chip joints depending on the materials used for mounting the RFID chip structures. X‐ray inspection and cross sectioning were performed to verify the quality of the assembly process. The microstructure and the resistance of the materials used for chip pads were investigated with the aim of determining the conductivity mechanism in the printed layers.

Addition of carbon nanotubes to the conductive adhesive (CA) provided a higher shear force for the assembled RFID chips, compared to the unmodified conductive adhesive or a polymer paste with silver flakes. However, this additive resulted in an increase in the material's resistance. It was found that the RFID substrate material had a significant influence on the shear force of mounted chips, contrary to the materials used for printing antennas. The lower shear force for chips assembled on antennas printed on paper rather than on foil was probably connected with its higher absorption of solvent from the pastes. Increasing the curing temperature and time resulted in an additional increase in the shear force for chips assembled to antennas printed on foil. A reverse dependence was observed for chips mounted on the antennas made on paper. An improvement in the durability of the RFID chip structures was achieved by chip encapsulation. Bending tests showed that a low‐melting adhesive was the best candidate for encapsulation, as it provided flexibility of the assembled structure.

Further studies are necessary to investigate the mechanical durability of RFID chips assembled with a conductive adhesive, with different addition levels and types of carbon nanotubes.

The results revealed that the best candidate for providing the highest RFID chip durability related to mechanical stresses was the low‐melting adhesive. It can be recommended for practical use, as it simplified the assembly process and reduced the curing step in the encapsulation of the RFID devices. From the results of shear testing, conductive adhesives with carbon nanotubes can be used in RFID chip assembly because of their ability to increase the shear force of joints created between the antenna and the chip.

In this paper, the influence of the materials used for antenna, chip pads, encapsulation and the curing conditions on the mechanical durability (shear and bending) of RFID chips was analyzed. Commercial and elaborated materials were compared. Some new materials containing a conductive adhesive and carbon nanotubes were proposed and tested in RFID chip assembly to antennas printed on flexible substrates (paper and foil).

Increasing demand for integrated circuits has put emphasis on the need for flexibility and productivity in any system developed to assemble them into systems. Added problems are created by the IC's fragility, size variation and minuteness.

A review of state‐of‐the‐art technology pertinent to tape automated bonding (for fine pitch, high I/O, high performance, high yield, high volume and high reliability) is presented. Emphasis is placed on a new understanding of the key elements (for example, tapes, bumps, inner lead bonding, testing and burn‐in on tape‐with‐chip, encapsulation, outer lead bonding, thermal management, reliability and rework) of this rapidly moving technology.

The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips.

Methods to embed chips in flex include flip‐chip assembly and subsequent lamination, or the construction of a separate ultra‐thin chip package (UTCP) using spin‐on polyimides and thin‐film metallisation technology. Thinning and separation of the chips is done using a “dicing‐by‐thinning” method.

The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 μm package where also the 20 μm thick chip is bendable.

Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies.

Thinning down silicon chips to thicknesses of 25 μm and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates.

This paper discusses chip removal and replacement processes of flip chip assemblies (FCAs) on printed wiring boards (PWBs). The original chip connection is achieved via mass reflow as in a surface mount assembly process. The FCA interconnection is one involving a surrogate solder bump on a chip and a lower melt solder on the PWB pads that fuses with the bump during reflow. The chip removal process thus entails melting the lower melt solder locally using hot gas. The following considerations will be discussed in the paper: chip size, chip removal methodology, local vs mass reflow for replacement attachment, solder height, the impact of multiple reflows on the solder joint integrity of assemblies. The use of the flip chip rework machine to remove ball grid arrays (BGAs) and quad flatpacks (QFPs) will be briefly addressed.

This paper discusses processes of flip chip on FR‐4 using eutectic solder bumps with possible fewer process steps compared to the full assembly process. Some interesting results in terms of the reliability performance of flip chip on FR‐4 assemblies using eutectic solder have been obtained after an almost‐one‐year temperature cycling test. The process steps of underfilling and curing of underfill can be omitted when a suitable epoxy is used for encapsulation. When underfill is conducted, encapsulation is not necessarily needed from a reliability point of view.

The purpose of this study is to provide a micro-nano chip automatic alignment system. Used for micron and nanometer channel alignment of microfluidic chip.

In this paper, combined with the reconstructed micro–nanoscale Hough transform theory, a “clamp–adsorb–rotate” chip alignment method is proposed. The designed alignment system includes a microscopic identification device, a clamping device and a suction device. After assembly, the straightness of the linear slide rail in the horizontal and vertical directions was tested, respectively. The results show that in the horizontal and vertical directions, the linearity error of the linear slide is +0.29 and 0.30 µm, respectively, which meets the requirement of chip alignment accuracy of 15 µm. In the direction of rotation, the angular error between the microchannel and the nanochannel is ±0.5°. In addition, an alignment flow experiment of the chip is designed. The results demonstrate that the closer the angle between the microchannel and the nanochannel is to 90°, the fluid fills the entire channel. Compared with the conventional method, the method and the assembly system realize fully automatic double-layer chip alignment.

A mechanical device designed by Hough transform theory can realize microfluidic chip alignment at nanometer and micron level.

The automatic alignment device adopts Hough transform principle and can be used for microfluidic chip alignment.