Precision Tin/Lead Alloy Plating for Flip‐Chip Mounting Technology

Abstract

Bumping is a prerequisite for flip‐chip attachment of bare dies. For silicon semiconductors bumping is normally performed on the ICs at wafer scale. Bumping can be performed by micro‐plating or vacuum deposition techniques. Mechanical methods are also well known. In this paper a bumping process based on tin/lead alloy plating is reported. The plating bath presented enables the deposition of both solder compositions used for flip‐chip attachment, the eutectic and the lead‐rich. All key issues of the plating process covering plating equipment, electrolyte characteristics and plating process parameters are discussed. Methods of bump characterisation and quality assurance are reported as an important part of the bumping process. The deciding process parameters leading to high quality solder bumps are demonstrated.

Citation

Richter, H., Ruess, K., Gemmler, A. and Leonhard, W. (1997), "Precision Tin/Lead Alloy Plating for Flip‐Chip Mounting Technology", Microelectronics International, Vol. 14 No. 1, pp. 9-13. https://doi.org/10.1108/13565369710800420