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The purpose of this paper is to present and apply a parasitic extraction approach for the calculation of DC busbar inductances.

A computational approach based on the finite integration technique and computed magnetic energy is developed to extract parasitic inductances. The finite integration analysis is conducted via the magnetoquasistatic solver of CST EM Studio^® capturing the 3D geometrical effects of the design, as well as the skin and proximity effects.

The method is applied successfully to evaluate the leakage inductances of two printed circuit boards structures; a backplane sample for the verification purpose and a real DC bus employed in a three‐phase pulse width modulation inverter.

The paper demonstrates that the method calculates the loop inductances accurately. It does not, however, verify the used technique to split loop inductances into partial inductances.

The extraction method is easy‐to‐use and able to handle complex geometries within acceptable computation time and accuracy.

The paper introduces a way to compute the parasitic inductances from the results of a numerical electromagnetic field solver.

The purpose of this paper is to study the high-frequency impacts of fast switching wide-bandgap transistors on electronic and motor designs. The high-frequency power converters, dedicated to driving high-speed motors, require specific models to design predictively electronic and motors.

From magnetic and electric models, the high-frequency parasitic elements for both electronics and motor are determined. Then, high-frequency circuit models accounting for of parasitic element extractions are built to study the wide bandgap transistors commutations and their impacts on motor windings.

The results of the models, for electronics and motors, are promising. The high-frequency commutation cell study is used to optimize the layouts and to improve the commutation behaviours and performances. The impact of the switching speed is highlighted on the winding voltage susceptibility. Then, the switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics. The electronic model is validated by experimentations.

The method can be only applied to the existing motor and electronic designs. It is not taken into account in an automized global high-frequency optimizer.

Helped by magnetic and electric FEA calculations where the parasitic element extractions are performed. The switching frequency and commutation rapidity can be both optimized to increase the performance of motor and electronics.

The purpose of this paper is to present the high-frequency performance of 0.13-μm n-type metal-oxide-semiconductor (NMOS) transistors with various multi-finger configurations for implementation in millimeter-wave (mm-wave) frequency.

A folded-like double-gate transistor layout is designed to enable the transistor to work in the mm-wave region. Different sizes of transistors with variation in finger width (W_F ) and number of fingers (N_F ) were fabricated to determine the optimum size of the transistor. The extrinsic parasitic elements of selected transistors were extracted and investigated. The radio frequency (RF) performance of these samples were then analyzed and compared.

The proposed layout performed well with the highest maximum oscillation frequency (f_max ) achieved at 122 GHz. Based on the comparison done, the optimum W_F obtained for the layout is at 2.0 μm. It is found that the extrinsic parasitic capacitance is more dominant than the parasitic resistance in affecting the f_max . In s-parameter analysis, it is observed that the transistor with the least N_F has smaller variance in small-signal gain throughout the measurement frequency. The maximum stable gain for the samples is also found to be roughly similar and independent of N_F .

A new layout structure for an NMOS transistor that works in mm-wave frequency is proposed. Experimental analyses presented here cover for both N_F and W_F , unlike others which focus on either N_F or W_F only.

Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.

The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.

Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.

This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.

To simulate large parasitic resistive networks, one must reduce the size of the circuit models through methods that are accurate and preserve terminal connectivity and network sparsity. The purpose here is to present such a method, which exploits concepts from graph theory in a systematic fashion.

The model order reduction problem is formulated for parasitic resistive networks through graph theory concepts and algorithms are presented based on the notion of vertex cut in order to reduce the size of electronic circuit models. Four variants of the basic method are proposed and their respective merits discussed.

The algorithms proposed enable the production of networks that are significantly smaller than those produced by earlier methods, in particular the method described in the report by Lenaers entitled “Model order reduction for large resistive networks”. The reduction in the number of resistors achieved through the algorithms is even more pronounced in the case of large networks.

The paper seems to be the first to make a systematic use of vertex cuts in order to reduce a parasitic resistive network.

The purpose of this paper is to offer a fast and accurate simulation method for printed spiral radio frequency identification coils and to extract the parameters of an equivalent resonance circuit.

The frequency‐dependent port impedance of a rectangular spiral multi‐turn antenna is simulated with the non‐retarded partial element equivalent circuit (PEEC) method. The discretization settings needed for an accurate modeling of skin and proximity effects at medium frequencies as well as parasitic capacitances are discussed. Two different PEEC approaches are used, a magneto‐quasi‐static (resistive and inductive cells) model and a non‐retarded (capacitive cells included) model in order to extract a reduced equivalent resonance circuit which is beneficial to describe the inductive coupling to further inductors via the transformer concept.

With optimized mesh settings, the extremely fast simulation can be carried out just in seconds whereas the results compared to a computationally much more expensive CST Microwave Studio^® reference solution as well as an analytical direct current solution show errors of only about a few percent.

The methodology is limited to frequencies up to the first self‐resonant frequency of the coil. In addition, piecewise‐homogeneous materials are implied.

Specialized mesh settings allow for a very fast and accurate simulation of rectangular spiral inductors. A method for the parameter extraction of a resonance circuit is proposed by evaluating two different PEEC models.

The purpose of this paper is to explore the functioning of very‐large‐scale integration (VLSI) interconnects and modeling of interconnects and evaluate different approaches of testing interconnects.

In the past, on‐chip interconnect wires were not considered in circuit analysis except in high precision analysis. Wiring‐up of on‐chip devices takes place through various conductors produced during fabrication process. The shrinking size of metal‐oxide semiconductor field effect transistor devices is largely responsible for growth of VLSI circuits. With deep sub‐micron (DSM) technology, the interconnect geometry is scaled down for high wiring density. The complex geometry of interconnects and high operational frequency introduce wire parasitics and inter‐wire parasitics. These parasitics causes delay, power dissipation, and crosstalk that may affect the signal integrity in VLSI system. Accurate analysis, sophisticated design, and effective test methods are the requirement to ensure the proper functionality and reliability of VLSI circuits. The testing of interconnect is becoming important and a challenge in the current technology.

The effects of interconnect on signal integrity, power dissipation, and delay emerges significantly in DSM technology. For proper performance of the circuit, testing of interconnect is important and emerging challenge in the nanotechnology era. Although some work has been done for testing of interconnect, however, it is still an open area to test the parasitics effects of VLSI/ultra‐large‐scale integration interconnects. Efforts are required to analyze and to develop test methods for crosstalk, delay and power dissipation in current technology with solutions to minimize this effect.

This paper reviews the functioning of VLSI interconnects from micrometer to nanometer technology. The development of various interconnect models from simple short circuit to latest resistance inductance capacitance transmission line model are discussed. Furthermore, various methodologies such as built‐in self test and other techniques for testing interconnect for crosstalk and delay are discussed.

New analytical approximation for the frequency‐dependent impedance matrix components of symmetric VLSI interconnect on lossy silicon substrate are derived. The results have been obtained by using an approximate quasi‐magnetostatic analysis of symmetric coupled microstrip on‐chip interconnects on silicon. We assume that the magnetostatic field meets the boundary conditions of a single isolated infinite line; therefore, the boundary conditions for the conductors in the structure are approximately satisfied. The derivation is based on the approximate solution of quasi‐magnetostatic equations in the structure (dielectric and silicon semi‐space), and takes into account the substrate skin‐effect. Comparisons with published data from circuit modeling or full‐wave numerical analyses are presented to validate the inductance and resistance expressions derived for symmetric coupled VLSI interconnects. The analytical characterization presented in this paper is well situated for inclusion into CAD codes in the design of RF and mixed‐signal integrated circuits on silicon.