Effects of process variation in VLSI interconnects – a technical review
Article publication date: 31 July 2009
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The purpose of this paper is to provide a comprehensive overview of types and sources of all aspects of interconnect process variations.
The impacts of these interconnect process variations on circuit delay and cross‐talk noises along with the two major sources of delays – parametric delay variations and global interconnect delays – have been discussed.
Parametric delay evaluation under process variation method avoids multiple parasitic extractions and multiple delay evaluations as is done in the traditional response surface method. This results in significant speedup. Furthermore, both systematic and random process variations have been contemplated. The systematic variations need to be experimentally modeled and calibrated while the random variations are inherent fluctuations in process parameters due to any reason in manufacturing and hence are non‐deterministic.
This paper usefully reviews process variation effects on very large‐scale integration (VLSI) interconnect.
Verma, K.G., Kaushik, B.K. and Singh, R. (2009), "Effects of process variation in VLSI interconnects – a technical review", Microelectronics International, Vol. 26 No. 3, pp. 49-55. https://doi.org/10.1108/13565360910981562
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