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The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture.

A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system.

The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images.

This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits.

The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering.

This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.

This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor.

Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths.

The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena.

The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

To explain the background and details and to discuss the implications of the USA Securities and Exchange Commission’s (SEC’s) July 23, 2014 amendments to Rule 2a-7 and other rules that govern money market funds under the Investment Company Act of 1940.

Explains the background, including problems during the financial crisis, the USA Treasury’s temporary guarantee program in 2008, earlier SEC proposals, and the USA Financial Stability Oversight Council’s recommendations. Details the amendments to Rule 2a-7, including the authorization to impose liquidity fees and redemption gates, the floating net asset value (NAV) requirement, the impact of the amendments on unregistered money funds operating under Rule 12d1-1, guidance on fund valuation methods, disclosure requirements, requirements for money fund portfolios to be diversified as to issuers of securities and guarantors, stress testing requirements, and compliance dates.

The Amendments set forth sweeping changes to money fund regulation and will have a profound effect on the money fund industry. Although the most significant provisions of the Amendments – the floating NAV requirement and the imposition of liquidity fees and redemption gates – will not go into effect for two years, the changes to the industry will be apparent almost immediately.

Money fund managers and boards of directors should begin assessing the potential impact of the Amendments and develop a schedule to come into compliance.

Practical guidance from experienced financial services lawyers.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process.

Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating.

Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack.

For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.

The purpose of this paper was to present the results of the three types of FG transistors that were investigated. The reliability issues of oxide thickness due to programming, fabrication defects and process variation may cause leakage currents and thus charge retention failure in the floating gate (FG).

The tunnelling and electron injection methods were applied to program FG devices of different lengths (180 and 350 nm) and coupling capacitor sizes. The drain current and threshold voltage changes were determined for both gate and drain voltage sweep. The devices were fabricated using IBM 130 nm process technology.

Current leakages are increasing with device scaling and reducing the charge retention time. During programming, charge traps may occur in the oxide and prevent further programming. Thus, the dominant factors are the reliability of oxide thickness to avoid charge traps and prevent current/charge leakages in the FG devices. The capacitive coupling (between the tunnelling and electron injection capacitors) may contribute to other reliability issues if not properly considered.

Although the results have raised further research questions, as revealed by certain reliability issues, they have shown that the use of FGs with nanoscale technology is promising and may be suitable for memory and switching applications.

This paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.

In the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.

The proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.

The research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate different architectural aspects and collect and provide our comparative evaluations.

Collecting over 40 IMC papers related to hardware design and optimization techniques of recent years, then classify them into three optimization option categories: optimization through graphic processing unit (GPU), optimization through reduced precision and optimization through hardware accelerator. Then, the authors brief those techniques in aspects such as what kind of data set it applied, how it is designed and what is the contribution of this design.

ML algorithms are potent tools accommodated on IMC architecture. Although general-purpose hardware (central processing units and GPUs) can supply explicit solutions, their energy efficiencies have limitations because of their excessive flexibility support. On the other hand, hardware accelerators (field programmable gate arrays and application-specific integrated circuits) win on the energy efficiency aspect, but individual accelerator often adapts exclusively to ax single ML approach (family). From a long hardware evolution perspective, hardware/software collaboration heterogeneity design from hybrid platforms is an option for the researcher.

IMC’s optimization enables high-speed processing, increases performance and analyzes massive volumes of data in real-time. This work reviews IMC and its evolution. Then, the authors categorize three optimization paths for the IMC architecture to improve performance metrics.

An understanding of reliability physics, failure analysis and failure mechanisms as applied to semiconductor technologies is essential in assessing microcircuit reliability. The use of valid thermal accelerated tests and the correct use of the data therefrom is crucial in assessing reliability. Improved technical data are required from most manufacturers if user analysis of accelerated testing is to be more easily and accurately carried out.

The purpose of this paper is to present a DNA hybridization detection sensor. An inexpensive fabrication procedure was used so that the sensors can be disposed economically after the measurement is completed.

Field effect transistor (FET) devices are used in the proposed structure. The FET device acts as a charge detection element and produces an amplified output current based on surface charge variations. As amplification is performed directly at the sensor frontend, noise sources have less effect on the detected signal, and thus, acceptably low DNA concentrations can be detected with simple external electronics. ZnO nano layers are used as the FET active semiconductor channel. Furthermore, a photobiasing approach is used to adjust the operating point of the proposed FET without the need for an additional gate terminal.

The proposed sensor is evaluated by applying matched and unmatched target DNA fragments on the fabricated sensors with capture probes assembled either directly on the ZnO surface or on a nano-platinum linker layer. It is observed that the presented approach can successfully detect DNA hybridization at the nano mole range with no need for complex laboratory measurement devices.

The presented photobiasing approach is effective in the adjustment of the sensor sensitivity and decreases the fabrication complexity of the achieved sensor compared with previous works.