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This study aims to regarding the application of traditional pulse frequency modulation control full-bridge LLC resonant converters in wide output voltage fields such as on-board chargers, there are issues with wide frequency adjustment ranges and low conversion efficiency.

To address these issues, this paper proposes a fixed-frequency pulse width modulation (PWM) control strategy for a full-bridge LLC resonant converter, which adjusts the gain by adjusting the duty cycle of the switches. In the full-bridge LLC converter, the two switches of the lower bridge arm are controlled by a fixed-frequency and fixed duty cycle, with their switching frequency equal to the resonant frequency, whereas the two switches of the upper bridge arm are controlled by a fixed-frequency PWM to adjust the output voltage. The operation modes of the converter are analyzed in detail, and a mathematical model of the converter is established. The gain characteristics of the converter under the fixed-frequency PWM control strategy are deeply analyzed, and the conditions for implementing zero-voltage switching (ZVS) soft switching in the converter are also analyzed in detail. The use of fixed-frequency PWM control simplifies the design of resonant parameters, and the fixed-frequency control is conducive to the design of magnetic components.

According to the fixed-frequency PWM control strategy proposed in this paper, the correctness of the control strategy is verified through simulation and the development and testing of a 500-W experimental prototype. Test results show that the primary side switches of the converter achieve ZVS and the secondary side rectifier diodes achieve zero-current switching, effectively reducing the switching losses of the converter. In addition, the control strategy reduces the reactive circulating current of the converter, and the peak efficiency of the experimental prototype can reach 95.2%.

The feasibility of the fixed-frequency PWM control strategy was verified through experiments, which has significant implications for improving the efficiency of the converter and simplifying the design of resonant parameters and magnetic components in wide output voltage fields such as on-board chargers.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.

Utilizing electrical discharge machining (EDM) to process micro-holes in superalloys may lead to the formation of remelting layers and micro-cracks on the machined surface. This work proposes a method of composite processing of EDM and ultrasonic vibration drilling for machining precision micro-holes in complex positions of superalloys.

A six-axis computer numerical control (CNC) machine tool was developed, whose software control system adopted a real-time control architecture that integrates electrical discharge and ultrasonic vibration drilling. Among them, the CNC system software was developed based on Windows + RTX architecture, which could process the real-time processing state received by the hardware terminal and adjust the processing state. Based on the SoC (System on Chip) technology, an architecture for a pulse generator was developed. The circuit of the pulse generator was designed and implemented. Additionally, a composite mechanical system was engineered for both drilling and EDM. Two sets of control boards were designed for the hardware terminal. One set was the EDM discharge control board, which detected the discharge state and provided the pulse waveform for turning on the transistor. The other was a relay control card based on STM32, which could meet the switch between EDM and ultrasonic vibration, and used the Modbus protocol to communicate with the machining control software.

The mechanical structure of the designed composite machine tool can effectively avoid interference between the EDM spindle and the drilling spindle. The removal rate of the remelting layer on 1.5 mm single crystal superalloys after composite processing can reach over 90%. The average processing time per millimeter was 55 s, and the measured inner surface roughness of the hole was less than 1.6 µm, which realized the  micro-hole machining without remelting layer, heat affected zone and micro-cracks in the single crystal superalloy.

The test results proved that the key techniques developed in this paper were suite for micro-hole machining of special materials.

The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.

This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.

Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.

According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.

Based on previous results of the existence, uniqueness, and regularity conditions for a continuous dynamic model for a parallel-plate electrostatic micro-electron-mechanical-systems with the fringing field, the purpose of this paper concerns a Galerkin-FEM procedure for deformable element deflection recovery. The deflection profiles are reconstructed by assigning the dielectric properties of the moving element. Furthermore, the device’s use conditions and the deformable element’s mechanical stresses are presented and discussed.

The Galerkin-FEM approach is based on weighted residuals, where the integrals appearing in the solution equation have been solved using the Crank–Nicolson algorithm.

Based on the connection between the fringing field and the electrostatic force, the proposed approach reconstructs the deflection of the deformable element, satisfying the conditions of existence, uniqueness and regularity. The influence of the electromechanical properties of the deformable plate on the method has also been considered and evaluated.

The developed analytical model focused on a rectangular geometry.

The device studied is suitable for industrial and biomedical applications.

This paper proposed numerical approach characterized by low CPU time enables the creation of virtual prototypes that can be analyzed with significant cost reduction and increased productivity.

This study aims to provide a comprehensive review of electric tugboat deployment in maritime transportation, including an in-depth assessment of its advantages and disadvantages. Along with the identification of advantages and disadvantages of electric tugboat deployment, the present research also aims to provide managerial insights into the economic viability of different tugboat alternatives that can guide future investments in the following years.

A detailed literature review was conducted, aiming to gain broad insights into tugboat operations and focusing on different aspects, including tugboat accidents and safety issues, scheduling and berthing of tugboats, life cycle assessment of diesel tugboats and their alternatives, operations of electric and hybrid tugboats, environmental impacts and others. Moreover, a set of interviews was conducted with the leading experts in the electric tugboat industry, including DAMEN Shipyards and the Port of Auckland. Econometric analyses were performed as well to evaluate the financial viability and economic performance of electric tugboats and their alternatives (i.e. conventional tugboats and hybrid tugboats).

The advantages of electric tugboats encompass decreased emissions, reduced operating expenses, improved energy efficiency, lower noise levels and potential for digital transformation through automation and data analytics. However, high initial costs, infrastructure limitations, training requirements and restricted range need to be addressed. The electric tugboat alternative seems to be the best option for scenarios with low interest rate values as increasing interest values negatively impact the salvage value of electric tugboats. It is expected that for long-term planning, the electric and hybrid tugboat alternatives will become preferential since they have lower annual costs than conventional diesel tugboats.

The outcomes of this research provide managerial insights into the practical deployment of electric tugboats and point to future research needs, including battery improvements, cost reduction, infrastructure development, legislative and regulatory changes and alternative energy sources. The advancement of battery technology has the potential to significantly impact the cost dynamics associated with electric tugboats. It is essential to do further research to monitor the advancements in battery technology and analyze their corresponding financial ramifications. It is essential to closely monitor the industry’s shift toward electric tugboats as their prices become more affordable.

The maritime industry is rapidly transforming and facing pressing challenges related to sustainability and digitization. Electric tugboats represent a promising and innovative solution that could address some of these challenges through zero-emission operations, enhanced energy efficiency and integration of digital technologies. Considering the potential of electric tugboats, the present study provides a comprehensive review of the advantages and disadvantages of electric tugboats in maritime transportation, extensive evaluation of the relevant literature, interviews with industry experts and supporting econometric analyses. The outcomes of this research will benefit governmental agencies, policymakers and other relevant maritime transportation stakeholders.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

The purpose of this study is to stabilize the rotating speed of the permanent magnet direct current (PMDC) motor driven by a DC-DC boost converter under mismatched disturbances (i.e.) under varying load circumstances like constant, frictional, fan type, propeller and undefined torques.

This manuscript proposes a higher order sliding mode control to elevate the dynamic behavior of the speed controller and the robustness of the PMDC motor. A second order classical sliding surface and proportional-integral-derivative sliding surface (PIDSS) are designed and compared.

For the boost converter with PMDC motor, both simulation and experimentation are exploited. The prototype is built for an 18 W PMDC motor with field programmable gate arrays. The suggested sliding mode with second order improves the robustness of the arrangement under disturbances with a wide range of control. Both the simulation and experimental setup shows satisfactory results.

According to software-generated mathematical design and experimental findings, PIDSS exhibits excellent performance with respect to settling speed, steady-state error and peak overshoot.

In this paper, a new front end converter (FEC) topology has been proposed for the switched reluctance (SR) motor drive. This study aims to present the performance analysis of FEC-based SR motor drive using various types of control schemes like conventional proportional integral (PI) controller, fuzzy logic controller (FLC) and fuzzy-tuned proportional integral controller (Fuzzy-PI).

The proposed FEC-based SR motor drive with various control strategies is derived for the torque ripple minimization and speed control.

The steady state and the dynamic response of the FEC-based SR motor drive are analyzed using three different controllers under change in speed and loading conditions. The Fuzzy-PI-based control scheme improves the dynamic response of the system when compared with the FLC and the conventional PI controller.

The hardware prototype has been implemented for the FEC-based SR motor drive by using the Xilinx SPARTAN 6 FPGA processor. The experimental verification has been conducted and the results have been measured under steady state and dynamic conditions.