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This study aims to solve the problem of high output voltage fluctuation and low efficiency caused by the misalignment of the magnetic coupling structure in the wireless charging system for electric vehicles. To address these issues, this paper proposes a dual LCC-S wireless power transfer (WPT) system based on the double-D double-layer quadrature (DDDQ) coil, which can realize the anti-misalignment constant voltage output of the system.

First, this paper establishes the equivalent circuit of a WPT system based on dual LCC-S compensation topology and analyzes its constant-voltage output characteristics and the relationship between system transmission efficiency and coupling coefficient. 1. Quadruple D (Ahmad et al., 2019) and double-D quadrature pad (DDQP) (Chen et al., 2019) coils have good anti-misalignment in the transverse and longitudinal directions, but the magnetic induction intensity in the center of the coils is weak, making it difficult for the receiving coil to effectively couple to the magnetic field energy. 2. Based on the double-D quadrature (DDQ) structure coil that can eliminate the mutual inductance between coupling coils and cross-coupling, Gong et al. (2022a) proposed a parameter optimized LCC-LC series-parallel hybrid topology circuit, which ensures that the output current fluctuation is controlled within 5% only when the system is misaligned within the 50% range along the X direction, achieving constant current output with anti-misalignment. The magnetic coupling structure’s finite element simulation model is established to analyze the change in magnetic induction intensity and the system’s anti-misalignment characteristics when the coil offsets along the x and y axes. Finally, an experimental prototype is developed to verify the constant voltage output performance and anti-misalignment performance of the system, and the proposed anti-misalignment system is compared with the systems in existing literature, highlighting the advantages of this design.

The experimental results show that the system can achieve a constant voltage output of 48V under a time-varying load, and the output voltage fluctuates within ±5% of the set value within the range of ±60 mm lateral misalignment and ±72 mm longitudinal misalignment.

Based on the dual LCC-S WPT system, the mutual inductance between the same side coils is reduced by adding decoupling coils, and the anti-misalignment characteristics and output power of the system are improved in a certain range. It is aimed at improving the stability of the system output and transmission efficiency.

This study aims to regarding the application of traditional pulse frequency modulation control full-bridge LLC resonant converters in wide output voltage fields such as on-board chargers, there are issues with wide frequency adjustment ranges and low conversion efficiency.

To address these issues, this paper proposes a fixed-frequency pulse width modulation (PWM) control strategy for a full-bridge LLC resonant converter, which adjusts the gain by adjusting the duty cycle of the switches. In the full-bridge LLC converter, the two switches of the lower bridge arm are controlled by a fixed-frequency and fixed duty cycle, with their switching frequency equal to the resonant frequency, whereas the two switches of the upper bridge arm are controlled by a fixed-frequency PWM to adjust the output voltage. The operation modes of the converter are analyzed in detail, and a mathematical model of the converter is established. The gain characteristics of the converter under the fixed-frequency PWM control strategy are deeply analyzed, and the conditions for implementing zero-voltage switching (ZVS) soft switching in the converter are also analyzed in detail. The use of fixed-frequency PWM control simplifies the design of resonant parameters, and the fixed-frequency control is conducive to the design of magnetic components.

According to the fixed-frequency PWM control strategy proposed in this paper, the correctness of the control strategy is verified through simulation and the development and testing of a 500-W experimental prototype. Test results show that the primary side switches of the converter achieve ZVS and the secondary side rectifier diodes achieve zero-current switching, effectively reducing the switching losses of the converter. In addition, the control strategy reduces the reactive circulating current of the converter, and the peak efficiency of the experimental prototype can reach 95.2%.

The feasibility of the fixed-frequency PWM control strategy was verified through experiments, which has significant implications for improving the efficiency of the converter and simplifying the design of resonant parameters and magnetic components in wide output voltage fields such as on-board chargers.

Adoption of integrated MOS based pseudo-resistor (PR) structures instead of using off-chip passive poly resistors for analog circuits in complementary metal oxide semiconductor technology (CMOS) is an area-efficient way for realizing larger time constants. However, issue of common-mode voltage shifting and excess dependency on the process and temperature variations introduce nonlinearity in such structures. So there is dire need to not only closely look for the origin of the problem with the help of a thorough mathematical analysis but also suggest the most suitable PR structure for the purpose catering broadly to biomedical analog circuit applications.

In this work, incremental resistance (IR) expressions and IR range for balanced PR (BPR) structures operating in the subthreshold region have been closely analyzed for broader range of process-voltage-temperature variations. All the post-layout simulations have been obtained using BSIM3V3 device models in 0.18 µm standard CMOS process.

The obtained results show that the pertinent problem of common-mode voltage shifting in such PR structures is completely resolved in scaled gate linearization and bulk-driven quasi-floating gate (BDQFG) BPR structures. Among all BPR structures, BDQFG BPR remarkably shows constant IR value of 1 TΩ over −1 V to 1 V voltage swing for wider process and temperature variations.

Various balanced PR design techniques reported in this work will help the research community in implementing larger time constants for analog-mixed signal circuits.

The PR design techniques presented in the present piece of work is expected to be used in developing tunable and accurate biomedical prosthetics.

The BPR structures thoroughly analyzed and reported in this work may be useful in the design of analog circuits specifically for applications such as neural signal recording, cardiac electrical impedance tomography and other low-frequency biomedical applications.

Conventional isolated dc–dc converters offer an efficient solution for performing voltage conversion with a large improved voltage gain. However, the small-signal analysis of these converters shows that a right-half-plane (RHP) zero appears in their control-to-output transfer function, exhibiting a nonminimum-phase stability. This RHP zero can limit the frequency response and dynamic specifications of the converters; therefore, the output voltage response is sluggish. To overcome these problems, the purpose of this study is to analyze, model and design a new isolated forward single-ended primary-inductor converter (IFSEPIC) through RHP zero alleviation.

At first, the normal operation of the suggested IFSEPIC is studied. Then, its average model and control-to-output transfer function are derived. Based on the obtained model and Routh–Hurwitz criterion, the components are suitably designed for the proposed IFSEPIC, such that the derived dynamic model can eliminate the RHP zero.

The advantages of the proposed IFSEPIC can be summarized as: This converter can provide conditions to achieve fast dynamic behavior and minimum-phase stability, owing to the RHP zero cancellation; with respect to conventional isolated converters, a larger gain can be realized using the proposed topology; thus, it is possible to attain a smaller operating duty cycle; for conventional isolated converters, transformer core saturation is a major concern, owing to a large magnetizing current. However, the average value of the magnetizing current becomes zero for the proposed IFSEPIC, thereby avoiding core saturation, particularly at high frequencies; and the input current of the proposed converter is continuous, reducing input current ripple.

The key benefits of the proposed IFSEPIC are shown via comparisons. To validate the design method and theoretical findings, a practical implementation is presented.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

This paper aims to obtain a symmetrical step-down topology with lower equivalent capacity and wider step-down range under the condition of the same output. Two new symmetrical step-down topologies of star-connected autotransformers are proposed in this paper. Taking the equivalent capacity as the main parameter, the obtained topologies are modeled and analyzed in detail.

This paper adopts the research methods of design, modeling, analysis and simulation verification. First, the star-connected autotransformer is redesigned according to the design objective of symmetrical step-down topology. In addition, the mathematical model of two topologies is established and a detailed theoretical analysis is carried out. Finally, the theoretical results are verified by simulation.

Two symmetrical star-connected autotransformer step-down topologies are designed, the winding configurations of the corresponding topology are presented, the step-down ranges of these three topologies are calculated and the influence of step-down ratio on the equivalent capacity of autotransformer are analyzed. Through analysis, the target step-down topologies are obtained when the step-down ratio is [1.1, 5.4] and [1.1, 1.9] respectively.

Because the selected research object is only a star-connected autotransformer, the research results may lack generality. Therefore, researchers are encouraged to further study the topologies of other autotransformers.

This paper includes the implications of the step-down ratio on the equivalent capacity of autotransformers and the configuration of transformer windings.

The topologies designed in this paper enable star-connected autotransformer in the 12-pulse rectifier to be applied in step-down circumstances rather than situations of harmonic reduction only. At the same time, this paper provides a way that can be used to redesign the autotransformer in other multi-pulse rectifier systems, so that those transformers can be used in voltage regulation.

Selective jet electrodeposition (SJED) is an emerging additive manufacturing (AM) technology for realizing metallic components of nano and micro sizes. The deposited parts on the substrate form metallurgical bonding, so separating them from the substrate is an unsolved issue. Therefore, this paper aims to propose a method for separating the deposited micro parts from a sacrificial substrate. Furthermore, single and multi-bead optimization is performed to fabricate microparts with varying density.

A typical SJED process consists of a nozzle (to establish a column of electrolytes) retrofitted on a machine tool (to provide relative motion between substrate and nozzle) that deposits material atom-by-atom on a conductive substrate.

A comprehensive study of process parameters affecting the layer height, layer width and morphology of the deposited micro-parts has been provided. The uniformity in the deposited parts can be achieved with the help of low applied voltage and high scanning speed. Multi-bead analysis for the flat surface condition is experimentally performed, and the flat surface condition is achieved when the centre distance between two adjacent beads is kept at half of the width of a single bead.

Although several literatures have demonstrated that the SJED process can be used for the fabrication of parts; however, part fabrication through multi-bead optimization is limited. Moreover, the removal of the fabricated part from the substrate is the novelty of the current work.

This paper aims to introduce a new numerical model that predicts the flashover voltage (FOV) value in the presence of polluted air surrounding a high-voltage insulator. The model focuses on simulating the propagation of arcs and aims to improve the accuracy and reliability of FOV predictions under these specific conditions.

This arc propagation method connecting the high voltage fitting and the grounded insulator cap involves a two-step process. First, the electric field distribution in the vicinity of the insulator is obtained using finite element method analysis software. Subsequently, critical areas with intense electric field strength are identified. Random points within these critical areas are then selected as initial points for simulating the growth of electric arcs.

by increasing the electric voltage applied to the insulator fittings, the arc path is, step by step, generated until a breakdown occurs on the polluted air surrounding the insulator surface, and thus a prediction of the FOV value.

The proposed model for the FOV prediction can be a very interesting alternative to dangerous and costly experimental tests requiring an investment in time and materials.

Some works were done trying to reproduce discharge propagation but it was always with simplified models such as propagation in one direction from a point to a plane. The difficulty and the originality of the present work is the geometry complexity of the insulator with arc propagation in three distinct directions that will require several proliferation conditions.

High throughput and power efficient computing devices are highly essential in many autonomous system-based applications. Since the computational power keeps on increasing in recent years, it is necessary to develop energy efficient static RAM (SRAM) memories with high speed. Nowadays, Static Random-Access Memory cells are predominantly liable to soft errors due to the serious charge which is crucial to trouble a cell because of fewer noise margins, short supply voltages and lesser node capacitances.

Power efficient SRAM design is a major task for improving computing abilities of autonomous systems. In this research, instability is considered as a major issue present in the design of SRAM. Therefore, to eliminate soft errors and balance leakage instability problems, a signal noise margin (SNM) through the level shifter circuit is proposed.

Bias Temperature Instabilities (BTI) are considered as the primary technology for recently combined devices to reduce degradation. The proposed level shifter-based 6T SRAM achieves better results in terms of delay, power and SNM when compared with existing 6T devices and this 6T SRAM-BTI with 7 nm technology is also applicable for low power portable healthcare applications. In biomedical applications, Body Area Networks (BANs) require the power-efficient SRAM design to extend the battery life of BAN sensor nodes.

The proposed method focuses on high speed and power efficient SRAM design for smart ubiquitous sensors. The effect of BTI is almost eliminated in the proposed design.

The purpose of this paper is to design and construct an amplitude shift keying (ASK) modulator, which, using the digital binary modulating signal, controls a floating memristor emulator (MR) internally without the need for additional control circuits to achieve the ASK modulated wave.

A binary digital unipolar signal to be modulated is converted by a pre-processor circuit into a suitable bipolar modulating direct current (DC) signal for the control of the MR state, using current conveyors the carrier signal’s amplitude is varied with the change in the memristance of the floating MR. A high pass filter is then used to remove the DC control signal (modulating signal) leaving only the modulated carrier signal.

The results from the experiment and simulation are in agreement showed that the MR can be switched between two states and that a change in the carrier signals amplitude can be achieved by using an MR. Thus, showing that the circuit behavior is in line with the proposed theory and validating the said theory.

In this paper, the binary signal to be modulated is modified into a suitable control signal for the MR, thus the MR relies on the internal operation of the modulator circuit for the control of its memristance. An ASK modulation can then be achieved using a floating memristor without the need for additional circuits or signals to control its memristance.