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Demand and popularity of portable electronic devices are driving the designers to strive for higher speeds, long battery life and more reliable designs. Recently, an overwhelming interest has been seen in the problems of designing digital systems with low power at no performance penalty. Most of the very large-scale integration applications, such as digital signal processing, image processing, video processing and microprocessors, extensively use arithmetic operations. Binary addition is considered as the most crucial part of the arithmetic unit because all other arithmetic operations usually involve addition. Building low-power and high-performance adder cells are of great interest these days, and any modifications made to the full adder would affect the system as a whole. The full adder design has attracted many designer's attention in recent years, and its power reduction is one of the important apprehensions of the designers. This paper presents a 1-bit full adder by using as few as six transistors (6-Ts) per bit in its design. The paper aims to discuss these issues.

The outcome of the proposed adder architectural design is based on micro-architectural specification. This is a textual description, and adder's schematic can accurately predict the performance, power, propagation delay and area of the design. It is designed with a combination of multiplexing control input (MCIT) and Boolean identities. The proposed design features lower operating voltage, higher computing speed and lower energy consumption due to the efficient operation of 6-T adder cell. The design adopts MCIT technique effectively to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design.

The proposed adder circuit simulated results are used to verify the correctness and timing of each component. According to the design concepts, the simulated results are compared to the existing adders from the literature, and the significant improvements in the proposed adder are observed. Some of the drawbacks of the existing adder circuits from the literature are as follows: The Shannon theorem-based adder gives voltage swing restoration in sum circuit. Due to this problem, the Shannon circuit consumes high power and operates at low speed. The MUX-14T adder circuit is designed by using multiplexer concept which has a complex node in its design paradigm. The node drivability of input consumes high power to transmit the voltage level. The MCIT-7T adder circuit is designed by using MCIT technique, which consumes more power and leads to high power consumption in the circuit. The MUX-12T adder circuit is designed by MCIT technique. The carry circuit has buffering restoration unit, and its complement leads to high power dissipation and propagation delay.

The new 6-T full adder circuit overcomes the drawbacks of the adders from the literature and successfully reduces area, power dissipation and propagation delay.

This paper presents a novel design method for keyboard circuits. The purpose of this study is to enable a single-board computer with fewer pins to recognize a keyboard system consisting of a large number of switches. Through the study of different kinds of keyboard circuits, a general circuit schematic design method is abstracted. Several experiments are conducted to prove the feasibility of the proposed circuit design method.

Conventional circuit schematic diagrams are often limited to two-dimensional planes. Through investigating higher dimensional alternatives, this paper proposes to place components in high-dimensional geometry before connecting all components. A multi-pin switch construction method is proposed to allow the switches to be arranged on the vertices of high-dimensional geometry and be connected sequentially to form the keyboard system. This proposed system can allow a keyboard system consisting of a large number of switches to be recognized by a single-board computer with less available pins.

The design scheme proposed in this paper can read more switch states with limited Input/Output pins. With the increase of the number of Input/Output ports and pins, the number of simultaneously identifiable switches increases exponentially, which is suitable for sensor design of array type.

Compared with the classical keyboard circuits, the circuit designed using the proposed method will lead to a slightly longer recognition time for each key. This can be compensated by a single-board computer with a modestly higher clock speed.

The circuit schematic design method based on high-dimensional geometry is introduced for the first time. The feasibility of the proposed method is verified by the original experiments. The proposed approach is of importance in guiding the design of new analog and digital sensor circuit systems.

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.

This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.

The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.

Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.

Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.

BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.

FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator.

The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module.

The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature.

A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.

Flex‐rigid circuits have been used for many years, primarily by the military, as a method to reduce the size and increase the reliability of electronic systems. However, in today's emerging designs where high speed ASICs are often the dominant components, flex‐rigid circuit assemblies are now an attractive solution for providing high density transmission line interconnects from board to board. Much of today's circuitry is being committed to ASIC designs to increase both circuit density and speed. Following this path, designers are faced with the task of interconnecting high lead count SMT packages often with as many as 300 to 500 leads per device, each dissipating several watts. At these power densities conductive cooling through the circuit board is often a necessity, dictating the use of either metal cores or heat exchangers. To make efficient use of the core and minimise weight, designs generally require SMT packages to be mounted on both sides of the core with electrical communication from side to side. However, as more exotic core materials (carbon fibre matrix, beryllium, etc.) and liquid cooled heat exchangers are used, electrical communication through the core has become difficult, if not impossible, in some cases. Instead, high density flex‐rigid assemblies are used to partition the circuit, allowing the board to ‘fold’ over the core. This results in hundreds of signal lines that must cross the flex, obeying the electrical design rules dictated by the rigid sections to maintain impedance values and crosstalk margins. This paper focuses on recent work at AIT, producing high density flex‐rigid circuits using embedded discrete wiring technology to meet the above requirements. Using 0.0025 in. diameter polyimide insulated wire, as many as 100 lines per linear inch can pass over the flex region on a single layer. This generally results in a single flex layer where all wires can be referenced to a continuous ground plane from board to board. Controlled impedance is easily maintained due to the uniform wire geometry, and high frequency attenuation is significantly lower than on equivalent etch circuit designs due to the smooth surface finish on the wire. In addition, the high interconnection density offered by this technique reduces the overall thickness of the rigid sections, thereby minimising the thermal resistance to the core.

This paper, which will be published in two parts in consecutive issues of Circuit World, reproduces a chapter of the recently published book ‘Handbook of Printed Circuit Technology: New Processes, New Technologies’, edited by G. Herrmann and K. Egerer and published by Electrochemical Publications Ltd, Port Erin, Isle of Man.

Recent advancements in the domain of smart communication systems and technologies have led to the augmented developments for very large scale integrated circuit designs in electro-magnetic applications. Increasing demands for low power, compact area and superior figure of merit–oriented circuit designs are the trends of the recent research studies. Hence, to accomplish such applications intended for optical communications, the transimpedance amplifier (TIA) was designed.

In this research work, the authors present a multi-layer active feedback structure which mainly composes a transimpedance stage and a gain stage followed by a low pass filter. This structure enables to achieve improved input impedance and superior gain. A simplified cascaded amplifier has also been designed in a hierarchical topology to improvise the noise effect further. The proposed TIA has been designed using Taiwan Semiconductor Manufacturing Company 45 nm complementary metal oxide semiconductor technology. Moreover, the thermal noise has been analyzed at −3 dB bandwidth to prove the reduction in thermal noise with increase in frequency for most of the devices used in the designed circuit.

The proposed differential TIA circuit was found to obtain the transimpedance gain of 50.1 dBO without applying any external bias current which is almost 8% improvised as compared to the conventional circuit. In addition to this, bandwidth achieved was 2.15 GHz along with only 38 W of power consumption, which is reasonably 100 times improvised in comparison of conventional circuit. Hence, the proposed differential TIA is suitable for the low power optical communications applications intended to work on low supply voltage.

The designed work is done by authors in university lab premises and is not copied from anywhere. To the best of the authors’ knowledge, it is 100% original.

Increasing speeds combined with the level of integration that can be obtained with advanced IC technology has dramatically changed the interconnection requirements for high performance electronic systems. With much of today's circuitry being implemented in custom silicon, IC technology has allowed both a dramatic reduction in size and a tremendous increase in performance. However, in terms of the interconnection problem, the by‐product of advanced IC technology is a new generation of IC s that often require several hundred I/OS, exhibit rise times of 150 ps to 300 ps, and dissipate several watts per device. As demanding requirements are placed upon circuit boards, the complexity of the design task increases dramatically, since a working solution must simultaneously address interconnection density, signal integrity and thermal performance. This paper examines embedded discrete wiring technology as a high density solution that meets the requirements necessary for transporting high speed digital signals.

Testing has become one of the dominant costs in the process of bringing a product from initial conception to the market place. Because of this, it is now imperative that the impact of any technology change on the test process is considered at an early stage. In this light, the increasing trend towards the use of surface‐mounting techniques in the fabrication of electronic systems is examined, with particular emphasis on the consequences on product testing during design validation, manufacture and repair. The aim is to highlight areas in which new attitudes and replacements for traditional solutions will be needed if surface‐mounting techniques are to be as cost‐effective as possible.

In the never‐ending quest for speed, designers are now turning to digital GaAs integrated circuits both to extend the bandwidth of current designs and in some cases to generate a whole new class of products never before possible. The engineer well versed in high speed ECL design techniques generally understands the problems associated with this transfer to GaAs logic. However, even with the design task well defined, the exact solution for interconnecting devices is often difficult and stresses the capabilities of existing multilayer printed circuit techniques using conventional dielectric materials and processing. This paper examines the design task in detail, and will present recent developments in shielded discrete wiring techniques as a possible solution for GaAs packaging.