Search results

A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties.

This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias).

The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100  × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out.

This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

The tenting of via holes has been a controversial issue in the military arena for several years. This issue has gained importance with MIL‐STD‐2000's requirement that all circuitry and vias under components be coated to preclude entrapment of flux. This paper addresses this issue by evaluating the MIL‐Spec thermal shock reliability of solder mask as a hole fill material and as a via tent cover. The relationship of via hole to pad size on tent reliability and solder mask thickness is also investigated. This paper concludes that solder mask as a hole fill material will not pass military thermal shock requirements and that standard dry film solder mask is very sensitive to via hole and pad dimensions. The thinner and more flexible high conformance solder mask is the only material capable of passing MIL‐Spec thermal shock requirements for all via hole to pad relationships.

To propose a solution procedure to minimize/eliminate tombstoning defects in small chip components with different micro via‐in pad designs for high density module assembly.

Four different micro via‐in pad designs were compared (via‐hole diameter): ultra small via‐in pads (10 μm), small via‐in pads (20 μm) and large via‐in pads (60 μm), as well as designs with no via‐in pads and capped via‐in pads. Two process variables were also evaluated for the goal of achieving a high‐yield assembly solution in micro via‐in pad and lead‐free solder conditions. Potential factors such as the preheat conditions of the reflow profile and stencil aperture size, which might affect tombstoning in components with micro via‐in pads, were investigated.

The results indicated that the micro via‐in pad design significantly increased the tombstoning; thus, tombstoning did not occur in components with both no via‐in pads and capped via‐in pads. Capped via‐in pads exhibited the best results in preventing tombstoning and provided a wide process window for the selection of process parameters. The results showed that tombstoning was found to decrease with both increasing stencil opening ratio and use of reflow profile with long‐preheat condition.

The paper's findings provide certain process guidelines for high density module assemblies with via‐in pad design. The strategy is to prevent tombstoning by adopting capped via‐in pad design if possible when employing micro via‐in pad technology.

To study the photonic band‐gap (PBG) characteristics constructed by periodic conducting vias on various guided transmission‐line structures.

The finite difference time domain (FDTD) method is adopted to analyze various PBG via structures. Conventionally, PBG characteristics on guided‐wave structures, such as microstrip lines or coplanar waveguides (CPW), are constructed through a series of perforations on the ground plane(s). PBG characteristics can, however, also be realized through periodic arrangements of conducting vias located on the respective ground planes.

Through studies of the scattering parameters, it has been found that all analyzed PBG via structures exhibit strong band‐gap characteristics in a particular frequency range. Different harmonic patterns are also observed when the dimensional sizes of the conducting vias vary with respect to the PBG period.

Research has been mainly limited to study solely the PBG via structures, guided‐wave transmission lines. More studies may be conducted in analyzing the overall performance when they are combined with other microwave components.

The proposed PBG via structures can be applied to various microwave areas, ranging from signal suppressions in microelectronics and mobile communications, to electro‐magnetic interference studies in other practical electronic circuit structures.

The ideas of applying conducting vias on the guided‐wave transmission lines and the proposed via patterns to induce the PBG characteristics are the research's claim to originality one.

The purpose of this paper is to solve the issue of via filling and pattern plating simultaneously by concentration optimization of accelerator and leveler in the electroplating bath.

This paper designs a series of experiments to verify the performance of pattern plating with the via filling plating formula. Then the compositions of electroplating solution are optimized to achieve via filling and pattern plating simultaneously. Finally, the mechanism of co-plating for via and line is discussed in brief.

To achieve excellent performance for via filling and pattern plating simultaneously, proportion of additives are comprehensively considered in optimization of electroplating process. Effects of additives on the via filling and pattern plating should be taken into consideration, especially in achieving flat lines.

This paper discusses the different effects of accelerator and leveler on the via filling and the pattern plating, respectively. The process of co-plating for the via and the line is presented. The superfilling of via and the flat line are simultaneously obtained with the optimized via filling formula.

The demand for higher density circuit packs, limited mounting space, faster switching times and cost‐effective designs has encouraged designers to take another look at placing vias directly in the mounting pads of reflow soldered surface mounted components. The standard reasons for not putting vias in pads (V‐I‐P) such as solder wicking and joint integrity were addressed and found to be surmountable. A study was performed to investigate the effects that a via in the mounting pad(s) has on the solder joint of both discrete components and gull and J‐leaded ICs. The size of the via was varied as well as the location along the centre axis of the pad. It was found that the via diameter is a critical parameter while the via location has no noticeable effect on the solder joint. Different assembly methods were also investigated. Several of the assembled test boards are being subjected to thermal cycling to determine the joint reliability. The results of this study are reported in this document.

This paper describes a process for fabricating high density multilayer polyimide‐metal interconnect structures for packaging applications such as multichip carriers, flex circuits and multiconductor TAB tape. The process combines the advantages of a semi‐additive via process, such as the uniformity of the electroplated vias and the ability to produce vertical stacked‐up vias, with a processing sequence that does not require a temporary plating mask for vias or a planarisation/via‐top‐exposure step. The key idea behind the process is the fact that all of the circuitry in a multilayer interconnect is electrically connected to the upper conductor layer. This allows building the interconnect upside down on a temporary substrate using a continuous bottom level metallisation as an electrode for plating all level vias. This layer eventually becomes the upper conductor. After the processing is complete, the multilayer interconnect structure is either released from the temporary substrate, resulting in a multilevel multichip interconnect. After the multilevel structure is released, the continuous metal, which was on the bottom, is patterned with the upper conductor pattern, isolating the individual circuits. As an example, a process sequence for building a three‐metal‐layer substrate with 5 ?m by 30 ?m copper conductors, 50 ?m by 50 ?m square vias with 15 ?m interlayer polyimide is presented along with electrical test data. The process can be extended to producing mixed‐geometry multiconductor tape structures for TAB that result in tape frames with controlled conductor properties, and offer the potential for finer geometries for TAB fingers than are now available through conventional TAB tape processes.

Pb‐free soldering challenged printed circuit board (PCB) assembly with high temperature. The purpose of this paper is to explain the failure mechanism of printed circuit board (PCB) assembly with solder bubbles of vias to avoid the problems of via‐drilling defects and solder joint failure.

The failure of PCB vias with solder bubbles was investigated through cross sections and SEM microstructure inspection, TMA measurement, moisture absorption analysis and DSC measurement. The moisture absorption and CTE of FR4 laminate matched with manufacturing requirement to avoid the effects of solder bubbles. The effects of via drilling with a dull drill bit were compared to that with a new drill bit.

The moisture absorbed inside holes of via plating layers could be exposed to induce solder bubbles during Pb‐free soldering assembly and dull drill bits should be prevented during the drilling process to avoid the no‐bearing drilling effects.

The failure of PCB vias is not only involved in the voiding in solder joints but manufacturing processes of PCB. The paper designs an approach to analyse the properties of PCB materials and the drilling effects of vias to find out the mechanism resulting in solder bubbles of vias. The problem of drill bits should be considered to prevent the moisture absorbed in drilling vias with defects.

This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, sequential build up (SBU) technology has been adopted as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through‐holes and microvias are all attributes of these high density interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.

This chapter examines La Vía Campesina’s strategy of consolidating strategic alliances in its global struggle to build food sovereignty. After discussing some of La Vía Campesina’s initial challenges in working with nongovernmental organizations we focus on two case studies: first, La Vía Campesina’s work with Veterinarios Sin Fronteras, based in Spain, and second, the International Planning Committee on Food Sovereignty. In both cases we analyze some of the convergences and divergences experienced by the social actors in efforts to build strategic alliances.