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Emerging ‘chip‐size’ packages, and bare flip‐chips, require new substrate properties if high lead count chips are to be reliably interconnected on printed wiring boards and multichip modules at low cost. Blind via holes have been shown to increase interconnect density significantly without adding layers which contribute to high cost. Until recently, the use of blind vias has been limited to high‐end applications since standard fabrication methods, either sequential lamination or controlled depth drilling, are too slow and expensive for most high volume commercial applications. To maintain a low layer count while interconnecting higher I/O packages, commercial and consumer electronics require a substrate technology which supports high speed, micro‐via hole formation. This paper describes a process for fabricating high speed micro‐vias in dimensionally stable non‐woven Aramid reinforced laminates using laser ablation technology. Laser equipment capable of producing over 100 blind micro‐via holes per second is discussed. The process steps of hole cleaning and plating are reviewed, showing how existing PWB manufacturing technologies can be used. This process is compared with other methods of generating small holes and blind vias in printed wiring boards. In addition, requirements for flip‐chip and chip‐size packages, including a coefficient of thermal expansion of <10 ppm/°C and thin laminate dimensional stability of <0.03%, are explained.

Ball grid array (BGA) component packages challenge the circuit board design with signal routing and layout, creating in some cases extra board layers and added vias all resulting in increased costs for the printed circuit board (PCB). As component densities increase and microBGA (μBGA) and other fine pitch components become more common, microvia‐in‐pad technology will ease the transition to these fine pitch components. This paper presents and profiles a cost‐effective solution to interconnecting BGAs on PCBs using laser drilled blind vias connecting the outer three or more layers of a multilayer circuit board. Following a discussion on the design advantages, a comprehensive outline of the PCB fabrication process explores a new procedure for the rapid production of via‐in‐pad multi‐depth blind via laser drilling.

With SMD‐Technology, the first purpose of plated‐through holes—to fix the components to the board—is no longer relevant. The utilisation of blind vias, preferably in combination with buried vias, results in an extremely high interconnection and packaging density and in most cases in fewer signal layers. Technology problems like drilling with precisely controlled Z‐axis as well as through‐plating of blind vias have been overcome. Reliability tests have shown a substantially lower failure rate in thermal cycling tests for DENSTRATE® multilayers.

There are many advantages of microvia: it requires a much smaller pad, which saves the board size and weight; with microvia, more chips can be placed in less space or a smaller PCB, which results in a low cost; and with microvia, electrical performance improves due to a shorter pathway. Basically, there are five major processes for microvia formation: NC drilling; laser via fabrication including CO₂ laser, YAG laser, and excimer; photo‐defined vias, wet or dry; etch via fabrications including chemical (wet) etching and plasma (dry) etching; and conductive ink formed vias, wet or dry. This paper will discuss the materials and processes of these five major microvia formation methods. At the end, eight key manufacturers from Japan will be briefly illustrated for their research status and current capability of producing smallest microvia.

High‐density interconnect (HDI) continues to be the fastest growing segment of the printed circuit board (PCB) market. The purpose of this paper is to discuss the differences in designing HDI compared to conventional PCB multilayers. This is important for the challenging aspects of very high‐speed electronics that require care to control signal integrity and power integrity.

Eight new design principles were studied and illustrated with emphasis on how these differ from conventional PCB design.

HDI implementation can be improved 2X to 4X by employing these new design principles. Densities from 6‐12 in. per sq. inch to 18‐48 in. per sq. inch have been reported. Design time reductions of 50 percent and cost reductions of 30 percent were also seen.

This work was focused on the basic design principles and does not address electronics design automation tools or specific design steps. PCB design is a complex activity and readers are encouraged to obtain and use the references cited.

The paper describes various design and layout procedures that the authors have learned over the last 29 years involved in printed circuit design and fabrication. These principles can be combined with other innovations to enable a much more beneficial use of HDI technologies.

Ball grid arrays, chip‐sized grid arrays, direct chip attach and flip chip are packages which are increasingly penetrating the market. However, the challenge to PCB fabricators will be how to meet the need imposed by these packages in terms of increased circuit density. Shrinking traces and spaces certainly offer some relief, but traces below 3 mils on 2 mil core will not meet the signal integrity requirements of high speed logic. The real opportunity to increase density is the reduction of via diameters and the adoption of alternative via structures. Non‐drilled vias offer the newest opportunity to increase board density while also reducing costs and board thickness. This paper looks at twelve ‘build‐up technologies’ that all employ non‐drilled vias as well as buried and blind vias. The design rules, materials, manufacturing process, structures, reliability and applications of many of these will be examined and compared. Highlighted will be the application to PCMCIA card (PC card) design and fabrication. Finally, preliminary cost comparisons will be given in order to position these technologies against standard PCBs.

In the past three years, microvia drilling using laser technology has become the dominant method of producing blind vias smaller than 150μm. The ablation characteristics of the materials used in the manufacture of PWBs can be divided into three categories: organics, glass, and metals. Organics are composed of resins and epoxies commercially available from a variety of vendors. Two types of resins that are typically used for microvia formation in the telecommunication applications are resin coated copper foil^® (RCC or RCF) for subtractive PCB process, and thermal‐curing resin (TCR) for additive PCB process respectively. This paper details the basics of UV YAG laser capabilities, alignment techniques, plating tests, reliability tests, manufacturable microvia design rules, and production experiences.

The purpose of this paper is to solve the issue of via filling and pattern plating simultaneously by concentration optimization of accelerator and leveler in the electroplating bath.

This paper designs a series of experiments to verify the performance of pattern plating with the via filling plating formula. Then the compositions of electroplating solution are optimized to achieve via filling and pattern plating simultaneously. Finally, the mechanism of co-plating for via and line is discussed in brief.

To achieve excellent performance for via filling and pattern plating simultaneously, proportion of additives are comprehensively considered in optimization of electroplating process. Effects of additives on the via filling and pattern plating should be taken into consideration, especially in achieving flat lines.

This paper discusses the different effects of accelerator and leveler on the via filling and the pattern plating, respectively. The process of co-plating for the via and the line is presented. The superfilling of via and the flat line are simultaneously obtained with the optimized via filling formula.

The purpose of this paper is to identify and expand upon the understanding of the reliability of high density interconnect (HDI) technologies containing multi‐level microvia interconnections with 2, 3 or 4 stacked and staggered configured structures.

Microvia testing was performed with interconnect stress testing (IST) using a modified methodology documented in the IPC test methods manual TM650, Method 2.6.26, titled DC current induced thermal cycle test. The IST coupon designs utilize mathematical modeling, in combination with prior experience in the fields of printed wiring board (PWB) processing, chemistry, materials and statistics, to improve the sensitivity of testing.

Single and 2 stack microvias are generally the most robust type of copper interconnection used in HDI applications, 3 stack and 4 stack require greater discipline to assure product reliability. Ranking the inherent reliability of 3 stack and 4 stack structures to other interconnects like plated through holes, blind, or buried vias, may need to be reconsidered in future reliability test programs.

This work was focused on the reliability of bare board and does not address failure modes associated with the additional stresses applied to the microvia structures created by the devices and their associated solder joints formed during surface mount assembly and rework operations.

This paper was written to improve the understanding of various aspects of design and their influence on reliability for stacked and staggered microvia structures. The design function must understand the physical construction as a critical influence on microvia reliability that should be taken into consideration in parallel with the electrical requirements.

Microvias or high density interconnects (HDI) printed circuits are now being designed in ever increasing quantities. HDI brings some interesting new solutions to age‐old signal integrity (SI) concerns, and concerns that will grow as rise‐times continue to drop.This article focuses on five major areas of SI concerns—(1) noise: (a) noise‐reflections, (b) noise‐crosstalk, (c) noise‐simultaneous switching; (2) electro‐magnetic interference (EMI); (3) interconnect delays.In each case, HDI offers improvements and alternatives—but it is not a panacea. A couple of “cautions” are listed that can be a major stumbling block to HDI implementation, fortunately, they are not SI based. Important to SI is the materials used in HDI. Although not the focus of this article, the materials selected, as well as the dimensional stack‐up and PCB design rules, will influence SI and electrical performance (impedance, crosstalk and signal conditioning). Miniaturization provided by HDI will be a major contributor to SI performance.Finally, the SI example is also a case study in cost reduction. The “before” and “after” conditions are reviewed to emphasize the cost reduction and “time‐to‐market” advantages of HDI technology.