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The purpose of this paper is to solve the issue of via filling and pattern plating simultaneously by concentration optimization of accelerator and leveler in the electroplating bath.

This paper designs a series of experiments to verify the performance of pattern plating with the via filling plating formula. Then the compositions of electroplating solution are optimized to achieve via filling and pattern plating simultaneously. Finally, the mechanism of co-plating for via and line is discussed in brief.

To achieve excellent performance for via filling and pattern plating simultaneously, proportion of additives are comprehensively considered in optimization of electroplating process. Effects of additives on the via filling and pattern plating should be taken into consideration, especially in achieving flat lines.

This paper discusses the different effects of accelerator and leveler on the via filling and the pattern plating, respectively. The process of co-plating for the via and the line is presented. The superfilling of via and the flat line are simultaneously obtained with the optimized via filling formula.

This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, sequential build up (SBU) technology has been adopted as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through‐holes and microvias are all attributes of these high density interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.

The purpose of this paper is to present a clear picture of the key factors of blind via and through hole filling in electroplating, e.g. shape of via or hole, electroplating solution, process, as well as the developments of mechanisms and models.

First, the paper details the development trends and challenges of via filling. Then the research status of mechanisms, electroplating solutions, including base solution and additives, numerical model and mass transfer is described. Finally, through hole filling is briefly reviewed.

To achieve excellent via filling performance, the characteristics of the via or hole, the ratio of acid/copper, selection of additives and factors of mass transfer are comprehensively considered in terms of optimization of the electroplating process. It is beneficial to design vias with appropriate aspect ratios, to strengthen the adsorption of the accelerator in the via bottom, to inhibit the increase of surface copper thickness and to form butterfly-shaped copper in the centre of through holes. Optimized process parameters should be taken into consideration in superfilling.

The paper reviews different sets of additives, mechanisms and superfilling models for state-of-the-art via filling and the developments of filling for through holes.

The trend of electronic products toward lighter, thinner, and faster transmission is challenging the printed circuit board industry to incorporate high density interconnection technology (such as build‐up and semi‐additive processes). Micro stacked via is one technology utilized to produce high‐density structures. Dielectric resin, conductive paste or via plating are usually applied for the filling process. As compared with other filling methods, via filling plating technology has advantages in offering a shorter process and higher reliability. This paper discusses the influence of different equipment design, operating conditions and additives on via filling plating technology.

The purpose of this paper is to overview the effect of electroplating current wave forms on Cu filling of through‐silicon‐vias (TSV) for three‐dimensional (3D) packaging.

The paper takes the form of a literature review.

Effective TSV technology for 3D packaging involves various processes such as via formation, filling with conductive material, wafer thinning, and chip stacking. Among these processes, high‐speed via filling without defect is very important for applying the TSV process to industry with a lower production cost. In this paper, the effects of various current forms on Cu electroplating of TSV such as direct current (DC), pulse current (PC), pulse reverse current (PRC), and periodic pulse reverse current (PPR) are described in detail including recent studies.

TSV is a core technology for high density 3D packaging. This paper overviews the recent studies of various current forms on Cu‐filling of TSV.

The purpose of this paper is to present a summary of development work made in technical centres and on the subsequent customer qualification of copper filled through holes and blind microvias.

Various copper deposition parameters were investigated in a small‐scale production line which was then extended to full‐scale production qualification in a horizontal conveyorised system. Samples of substrates with copper filled through holes were qualified at end‐user facilities.

The copper plating process may be used to replace an existing production process for printed circuit boards. The proposed system can give a more reliable result in terms of filling and technical capability for the produced substrate. Overall production cost savings are possible.

The technology is based on a copper plating electrolyte using a redox pair for copper replenishment. The results achieved depend on use of this system and on production equipment which can control the redox system and copper concentration within a tight range.

The paper shows how the use of a horizontal production system with redox copper replenishment can achieve filling of though holes and blind microvias with reduced surface plated copper thickness. Reduction in the use of copper saves both resources and also reduces production costs. The process is proposed as an alternative to existing paste plugging processes, which are both cost and labour intensive.

Printed circut boards (PCBs) have diminished in size and, simultaneously, their circuit densities have increased. Conventional multi‐layered PCBs have a limitation to higher packaging densities. This paper introduces a new copper electroplating formula that is able to fill vias and through holes simultaneously and is used in a DC plating method, in which the copper thickness deposited on the board surface is relatively very thin after the electroplating is completed.

The purpose of this paper is to present the materials and process considerations and solutions that enable the safe use of plugging pastes in high density interconnection (HDI) printed circuit boards (PCBs) designed to operate at higher temperatures.

The paper introduces the concept of microvia plugging and the issues that are important in influencing HDI PCB reliability. Plugging pastes and their properties are discussed along with the various plugging processes that can be used. The advantages and disadvantages of each type of process are compared and contrasted.

The creation of via holes and the filling of these interconnection holes or buried vias and their subsequent copper plating is one of the key processes in HDI technology. In future, the importance of plugging will increase, particularly on account of the growing demand for copper plating and dimensional stability.

The paper highlights the importance of making the correct selection of materials and processing methodologies and details the implications of these choices.

The paper describes the different approaches that can be used for filling microvias and details the issues, advantages and disadvantages of the various approaches. The paper particularly focuses on the special demands on plugging pastes used in higher temperature range applications.

The purpose of this paper is to introduce a new copper electroplating formula which is able to fill blind microvias (BVHs) and through holes (THs) at one process through a direct current (DC) plating method.

Test boards of printed circuit board (PCB) fragments with BVHs and THs for filling plating are designed. The filling plating is conducted in a DC plating device, and the filling processes and influence factors on filling effect of BVHs and THs are investigated. Dimple depths, surface copper thickness, thermal shock and thermal cycle test are applied to characterize filling effect and reliability. In addition, to overcome thickness, increase of copper on board surface during filling plating of BVHs and THs, a simple process called pattern plating, is put forwarded; a four-layered PCB with surface copper thickness less than 12 μm is successfully produced.

The filling plating with the new copper electroplating formula is potential to replace the conventional filling process of BVHs and THs of PCB and, most importantly, the problem of thickness increase of copper on board surface after filling process is overcome if a pattern plating process is applied.

The dimple depth of BVHs and THs after filling plating is not small enough, though it meets the requirements, and the smallest diameter and largest depth of holes studied are 75 and 200 μm, respectively. Hence, the possibility for filling holes of much more small in diameter and large in depth with the plating formula should be further studied.

The paper introduces a new copper electroplating formula which achieves BVHs and THs filling at one process through a DC plating method. It overall reduces production processes and improved reliability of products resulting in production cost saving and production efficiency improvement.

This paper aims to deduce a set of theory computational formula, and optimize and improve the heat conductivity of vias in printed circuit boards of electrical power apparatus.

The authors adopted numerical simulation and experimental measurement to verify the reliability of this formula.

Research result showed that 0.45 mm was the optimal bore diameter of vias; the conductivity had no obvious improvement when filling material was FR4 or Rogers, but if it was filled with texture of high thermal conductivity like soldering tine, the conductivity would improve a lot; the plating thickness of vias had a greater influence on thermal conductivity.

Through the theory computational formula, this paper studied the influence of aperture of vias, filled materials and thickness of copper plated on vias on thermal conductivity.