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This paper presents a VHDL‐AMS based genetic optimisation methodology for fuzzy logic controllers (FLCs) used in complex automotive systems and modelled in mixed physical domains. A case study applying this novel method to an active suspension system has been investigated to obtain a new type of fuzzy logic membership function with irregular shapes optimised for best performance.

The geometrical shapes of the fuzzy logic membership functions are irregular and optimised using a genetic algorithm (GA). In this optimisation technique, VHDL‐AMS is used not only for the modelling and simulation of the FLC and its underlying active suspension system but also for the implementation of a parallel GA directly in the system testbench.

Simulation results show that the proposed FLC has superior performance in all test cases to that of existing FLCs that use regular‐shape, triangular or trapezoidal membership functions.

The test of the FLC has only been done in the simulation stage, no physical prototype has been made.

This paper proposes a novel way of improving the FLC's performance and a new application area for VHDL‐AMS.

The field of quality has undergone significant changes as reflected by changes in its definition, paradigms, approaches, techniques, and scope of application. This paper reviews emerging trends and issues focusing on quality engineering. Changes in customer expectation have driven the changes in the technology of design and manufacturing, which is becoming more important in satisfying individual customer expectations. This also calls for special attention to the engineering aspects of quality. Brief reviews on recent advances in the prominent quality tools such as statistical process control, quality function deployment, and design of experiment are reported. General trends in quality engineering research show the tools are being enhanced, integrated, computerized and broaden their application bases, where possible opportunities for further investigation are indicated. Among others these include contributions in multiple‐response optimization, intelligent quality systems, multivariate SPC, and practical and simple guidelines for actual implementation of various tools.

The purpose of this paper is to present the design of a piezoelectric vibration energy generator with a power conditioning circuit to power a wireless sensor node. Frequency and voltage characterization of the piezoelectric energy harvester is performed. A single-stage AC–DC power converter that integrates the rectification and boosting circuit is designed, simulated and implemented in hardware.

The designed power conditioning circuit incorporates bridgeless boost rectification, a lithium ion battery as an energy storage unit and voltage regulation to extract maximum power from PZT-5H and to attain higher efficiency. The sensor node is modelled in active and sleep states on the basis of the power consumption. Dynamic modelling of the lithium ion battery with its state of charging and discharging is analysed.

The test result shows that the energy harvester produces a maximum power of 65.9 mW at the resonant frequency of 21.4 Hz. The designed circuit will operate even at a minimum input voltage of 0.5 V. The output from the harvester is rectified, boosted to a 7-V DC output and regulated to 3.3 V to the power C_Mote wireless sensor node. The conversion efficiency of the circuit is improved to 70.03 per cent with a reduced loss of 19.76 mW.

The performance of the energy harvester and the single-stage power conditioning circuit is analysed. Further, the design and implementation of the proposed circuit lead to an improved conversion efficiency of 70.03 per cent with a reduced loss of 19.76 mW. The vibration energy harvester is integrated with a power conditioning circuit to power a wireless sensor node C_Mote. The piezoelectric vibration energy harvester is implemented in real time to power C_Mote.

A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.

This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.

The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.

This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements.

The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm.

All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR).

The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

In the paper, basing on the electromagnetic field analysis in a system with a thin conducting plate, infinitely extended, a set of equations approximately representing the boundary conditions on the plate is presented as well as the scope of their validity is estimated. Developing the idea announced in the eddy current problem is examined in a system with a thin plate having finite surface dimensions and with an external source of any configuration. The problem has been reduced to the Fredholm's equation of the second kind which, for regular‐shaped plates, can be solved in an explicite form Results of calculations are verified by experiment.

In the United States, students with disabilities have moved from learning in a segregated environment to being included in the general education classroom. Legislative mandates have encouraged this shift to occur in public schools in order to equal the playing field for students with disabilities. Both general and special education students with learning disabilities (LD) have been affected from inclusion. This chapter describes the legal, historical, psychological, and instructional concepts shaping the way students with LD are educated today.

Recent progress in the development of electromagnetic field theory and sophisticated software for solution of complicated, non‐linear, 3‐D structures is not always accompanied with relatively cheap and simply presented engineering instructions, easy to use for regular industrial design. In the paper some theoretical and practical examples are given as to how one can get over a excessive calculating difficulties to obtain quickly simple design directions and reduce complicated theory to simple practical conclusions. The fast and cheap package RNM‐3D is validated by comparison with industrial test data and with the interactive graphics system is the final illustration of the effectiveness of such an approach. RNM‐3D is used successfully in many transformer works the world over.

This paper aims to deal with the development of a software tool to simulate and study vehicle – road interaction (VRI) to quantify the forces induced and energy released from vehicles to the road pavement, in different vehicle motion scenarios, and the energy absorbed by the road surface, speed reducers or a specific energy harvester surface or device. The software tool also enables users to quantify the energetic efficiency of the process.

Existing software tools were analysed and its limitations were identified in terms of performing energetic analysis on the interaction between the vehicle and the road pavement elements, such as speed reducers or energy harvest devices. The software tool presented in this paper intends to overcome those limitations and precisely quantify the energy transfer.

Different vehicle models and VRI models were evaluated, allowing to conclude about each model precision: bicycle car model has a 60 per cent higher precision when compared with quarter-car model, and contact patch analysis model has a 67 per cent higher precision than single force analysis model. Also, a technical study was performed for different equipment surface shapes and displacements, concluding that these variables have a great influence on the energy released by the vehicle and on the energy harvested by the equipment surface.

The developed software tool allows to study VRI with a higher precision than existing tools, especially when energetic analyses are performed and when speed reduction or energy harvesting devices are applied on the pavement.

The present work aims to explain how the nonlinear average model can be used in power electronic integration design as a behavioral model.

The nonlinear average model is used in power electronic integration design as a behavioral model, where it is applied to a voltage source inverter based on IGBTs. This model was chosen because it takes into account the nonlinearity of the power semiconductor components and the wiring circuit effects, which can be formalized by the virtual delay concept. In addition, the nonlinear average model cannot distinguish between slow and quick variables and this is an important feature of the model convergence.

The paper studies extensively the construction of the nonlinear average model algorithm theoretically. Detailed explanations of the application of this model to voltage source inverter design are provided. The study demonstrates how this model illustrates the effect of the nonlinearity of the power semiconductor components' characteristics on dynamic electrical quantities. It also predicts the effects due to wiring in the inverter circuit.

More simulations and experimental analysis are still necessary to improve the model's accuracy, by using other static characteristic approaches, and to validate the applicability of the model to different converter topologies.

The paper formulates a simple nonlinear average model algorithm, discussing each step. This model was described by VHDL‐AMS. On the one hand, it will assist theoretical and practical research on different topologies of power electronic converters, particularly in power integration systems design such as the integrated power electronics modules (IPEM). On the other hand, it will give designers a more precise behavioral model with a simpler design process.

The nonlinear average model used in power electronic integration design as behavioral model is a novel approach. This model reduces computational costs significantly, takes physical effects into account and is easy to implement.