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The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.

An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.

FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm² of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.

The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

The purpose of this paper is to summarize several identification methods for the automatic commissioning of electrical drives that are presented in different earlier papers of the same authors. This paper is intended as a contribution to the development of expert systems, taking into account parametric models of the mechanical and electrical subsystem as well as the corresponding parameter fitting.

Some system parameters, which are mandatory for the commissioning of electrical and mechanical systems are often not known. For their identification, a method based on the frequency response calculation utilizing the Welch method is now presented. The main focus of the work is directed to the measurement of the frequency response by exciting the system with pseudo‐random binary signals and to the subsequent procedure for the calculation of the corresponding parameter by utilizing the Levenberg‐Marquardt algorithm.

The presented identification procedure leads to outstanding results during the commissioning of the system as well as under normal operation conditions. The identification of the parameter of the mechanical and electrical systems is therefore possible during the commissioning of the drive as well as in running machines. Further, some restrictions regarding the measurement facilities are presented.

The presented identification procedure can be applied in a variety of conditions and can be applied for diagnostic tasks. New measurement and considerations regarding the restrictions of the applied method also under normal operation of the systems underline this fact.

This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD).

The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process.

The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency.

The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

The purpose of this paper is to design and create a potentiostat that can be integrated and encapsulated within a microelectrode as a low‐cost electrochemical sensor. Recently, microsystems on sensors or lab on a chip using electrochemical detection of substances matters are pushing forward into the area of analysis. For providing electrochemical analysis, the microsystem has to be equipped with an integrated potentiostat.

The integrated potentiostat with four current ranges (from 1 μA to 1 mA) was designed in the CADENCE software environment using the AMIS CMOS 0.7 μm technology and fabricated under the Europractice program. Memory cells of 48 bytes are implemented with the potentiostat using VERILOG.

The characteristics of integrated potentiostat are strictly linear; the measured results confirm the simulated values. The potentiostat measurements error is about 1.5 percent and very low offsets are reached by the offset‐zeroing circuitry.

The detection limit of the current at the lowest range with respect to S/N ratio is about 10 nA.

The integrated potentiostat is embedded on a screen‐printed sensor and its characteristics are successfully verified. Lower range of 100 nA can be implemented on a new microchip as well as rail‐to‐rail output circuitry would increase the voltage dynamic range.

The integrated potentiostat with very good parameters is designed for a wide spectrum of electrochemical applications such as lab on a chip, embedded electrochemical systems, etc. The integrated system enables storing of information about the system measured, for instance, calibration and fabrication data of the electrochemical sensor.

Enterprise resource planning (ERP) offers a streamlined system architecture to feed businesses with beneficial information in the current intense global competition. The primary concern of ERP is how to integrate different functional units to facilitate a unified flow of information. This paper aims at providing a non-trivial practice of integrating the quality control (QC) system into the core ERP processes of a real large-scaled case study.

To satisfy the purpose of the current study, a large-scale steel making holding, inclusive of 27 business units being dispersed over a wide area, has been targeted. In our research methodology, a sample of four business units is selected as the pilot cases to be investigated at first. The output results of such investigations are further extended to the other units. In light of the investigation, the existing QC working conditions of the pilot cases are assessed through the As-Is model. The To-Be models are derived based on the best practices and the integration scope is then bordered.

The findings show that the integrated QC solution has enabled the following features: the smooth interconnection between QC and other functional units like purchase and manufacturing, the ease of generating real-time performance report of QC unit, the sack of tracing the quality of any available item in the system and the root-cause of defects, and the straightforwardness of the qualitative assessment of the suppliers.

There is almost no similar practice for designing a large-sized integrated system from scratch in the target region associated with our case study while the off-the-shelf products are prohibitively expensive.

This paper includes implications for providing a standard practice on integrating a substantial module of ERP down to the smallest detail.

The value of the current paper is associated with fulfilling a critical research gap in the context of studying the QC integration into an enterprise solution. In fact, despite the importance of the QC module and its plethora of interconnection with other functional units, the literature review shows a centric lack of considering such integration in a real case study, particularly the large-scale one. Further, this paper works as a valuable study in the literature owing to not only focusing on the design and development of an integrated QC solution but also considering the deployment facet of such a practice.

An automation project for linking knitted components has required development of a high‐speed vision sensing system

This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements.

The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm.

All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR).

The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

The purpose of this study is to examine and establish how sensemaking develops among a group of external change agents (ECAs) engaged to disseminate a national quality register nationwide in Swedish health care and elderly care. To study the emergent sensemaking, the theoretical concept of cognitive shift has been used.

The data collection method included individual semi-structured interviews, and two sets of interviews (initial sensemaking and renewed sensemaking) have been conducted. Based on a typology describing how ECAs interpret their work, structural analyses and comparisons of initial and renewed sensemaking are made and illuminated in spider diagrams. The data are then analyzed to search for cognitive shifts.

The ECAs’ sensemaking develops. Three cognitive shifts are identified, and a new kind of issue-related cognitive shift, the outcome-related cognitive shift, is suggested. For the ECAs to customize their work, they need to be aware of how they interpret their own work and how these interpretations develop over time.

The study takes a novel view of the interrelated concepts of sensemaking and sensegivers and points out the cognitive shifts as a helpful theoretical concept to study how sensemaking develops.

An improved structure for adiabatic pseudo‐domino logic (APDL) family is presented in this paper. The modified dual‐rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.

Systolic array designs of parallel algorithms for low‐level digital image processing, and in particular the gradient operator, are described. Indicates how, to achieve high performance, a new systolic array can be designed in which all the cells in a double pipeline are interconnected to a system bus. The transputer implementation of the design is also considered and comments and conclusions that relate to the use of the systolic array on transputer networks are given. Subsequently it is shown that the systolic array design can be extended to handle the Prewitt and Sobel operators.