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The purpose of this paper is to find a closed relation for the phase noise of LC oscillators.

The governing equation of oscillators is generally a stochastic nonlinear differential equation. In this paper, a closed relation for the phase noise of LC oscillators was obtained by approximating the I–V characteristic of the oscillator with third-degree polynomials and analyzing its differential equation.

This relation expresses phase noise directly in terms of circuit parameters, including the sizes of the transistors and the bias. Next, for evaluation, the phase noise of the cross-coupled oscillator without tail current was calculated with the proposed model. In this approach, the obtained equations are expressed independently of technology by combining the obtained phase noise relation and g_m/I_D method.

A technology-independent method using the g_m/I_D method and the closed relationship is provided to calculate phase noise.

Multiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.

The proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.

The introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.

This technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

The purpose of this paper is to design a low phase noise and high figure of merit, fully integrated, voltage‐controlled oscillator (VCO) which was fabricated in TSMC CMOS 0.18‐μm 1P6M process.

A differential PMOS cross‐coupled architecture VCO with the capacitive feedback technology was designed to increase the linearity of frequency tuning range and decrease the phase noise. Varactor determining the performance of tuning range is also a key component in the design of VCO. The authors adopt the accumulation‐mode MOS varactor. The output spectrum and the phase noise are measured by E5052A spectrum analyzer.

The VCO is successfully fabricated in TSMC RF CMOS 0.18um 1P6M process. The measured tuning range is from 10.875 GHz ∼ 11.1 GHz with control voltage from 0 to 1.5 V. The measured phase noise is as low as −120.42 dBc/Hz at 1 MHz offset and the high FOM is −189.5 dBc/Hz. The output spectrum is −10.51dBm with center oscillator frequency of 10.942 GHz. The core circuit without buffer consumes power of 15 mW from a 1.8 V supply voltage.

This paper shows a fully integrated CMOS LCVCO architecture using capacitive feedback technology with low phase noise and high figure of merit for OC‐192 SONET applications.

The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

This paper aims to detect small dynamic displacements by analysis of L1 Global Positioning System carrier frequency using an improved method for collecting data and filtering techniques on monitoring large structures. It is proposed to analyze the phase residuals directly from the raw phase observable data collected in a short baseline during a limited time span, in lieu of obtaining the residual data file from regular GPS processing programs.

The approach of this paper is an update on the method based on the interferometer idea for analyzing the Global Positioning Systems signals applying adaptive filtering techniques on the phase residuals computed through the double difference adjusted by the 3rd order polynomial. The method is based on the frequency domain analysis of the phase residuals resulted from the L1 double difference static data processing of only two satellites.

This research improves the ability to characterize the dynamic behavior of large structures though the detection of millimeter‐level data of structural amplitude oscillation response and its frequency value.

Support of Civil Engineers by collaboration on monitoring oscillations of spans and towers of large bridges; determination of amplitude oscillations value and low‐frequency modal values. The paper presents two trials to verify the proposed methodology for using GPS as a tool for monitoring large structures.

The paper presents a comprehensive framework and implementation approach to demonstrate the capabilities of Global Positioning System as a tool for monitoring large structures providing accurate response data at high levels of precision.

Wireless sensor networks (WSNs) are periodically collecting data through randomly dispersed sensors (motes), which typically consume high energy in radio communication that mainly leans on data transmission within the network. Furthermore, dissemination mode in WSN usually produces noisy values, incorrect measurements or missing information that affect the behaviour of WSN. In this article, a Distributed Data Predictive Model (DDPM) was proposed to extend the network lifetime by decreasing the consumption in the energy of sensor nodes. It was built upon a distributive clustering model for predicting dissemination-faults in WSN. The proposed model was developed using Recursive least squares (RLS) adaptive filter integrated with a Finite Impulse Response (FIR) filter, for removing unwanted reflections and noise accompanying of the transferred signals among the sensors, aiming to minimize the size of transferred data for providing energy efficient. The experimental results demonstrated that DDPM reduced the rate of data transmission to ∼20%. Also, it decreased the energy consumption to 95% throughout the dataset sample and upgraded the performance of the sensory network by about 19.5%. Thus, it prolonged the lifetime of the network.

The purpose of this paper is to examine existing radar sensor results, techniques for through‐wall radar and current applications for the technology.

The paper provides information on sensing through a high‐attenuation obstacle and the associated pitfalls and considerations. Results from ultra‐wide‐band (UWB) impulse radar, micro‐Doppler radar, and synthetic aperture radar (SAR) targeted at this area are presented. Discussion of radar clutter classification is given and also observations on presenting a system with a non‐zero false alarm rate to a user to give best confidence and maximum decision capability.

There are significant new requirements for through‐wall radar which a combination of UWB, continuous wave, and SAR techniques with recent signal processing advances and the advent of low‐cost radio and image processing can meet in distributed markets. Risk of a poor user level decision in a non‐zero‐false‐alarm‐rate system can be mitigated by increasing the number of inputs into the decision.

The paper lists challenges that have been overcome in the area of through‐wall sensing and presents results from novel radar sensors.

The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach.

This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplified average model and will show that following this approach, there is a mismatch between their actual and desired transient performance. A new PLL design method is then proposed based on the DPM approach that allows the development of fourth-order DPM models. The small-signal eigenvalues analysis of the fourth-order DPM models is used to determine the control gains and the stability limits.

The DPM approach is proven to be useful for single-phase PLLs stability analysis and control parameters design. It has been successfully used to design the control parameters and to predict the PLL stability limits, which have been validated via simulation and experimental tests consisting of grid voltage sag, phase jump and frequency step change.

This paper has introduced the use of DPM approach for the purpose of single-phase PLL stability analysis and control design. The approach has enabled accurate control gains design and stability limits identification of single-phase PLLs.

The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research.

This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO.

The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs.

Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it.

The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications.

The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.