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Wireless sensor networks (WSNs) are periodically collecting data through randomly dispersed sensors (motes), which typically consume high energy in radio communication that mainly leans on data transmission within the network. Furthermore, dissemination mode in WSN usually produces noisy values, incorrect measurements or missing information that affect the behaviour of WSN. In this article, a Distributed Data Predictive Model (DDPM) was proposed to extend the network lifetime by decreasing the consumption in the energy of sensor nodes. It was built upon a distributive clustering model for predicting dissemination-faults in WSN. The proposed model was developed using Recursive least squares (RLS) adaptive filter integrated with a Finite Impulse Response (FIR) filter, for removing unwanted reflections and noise accompanying of the transferred signals among the sensors, aiming to minimize the size of transferred data for providing energy efficient. The experimental results demonstrated that DDPM reduced the rate of data transmission to ∼20%. Also, it decreased the energy consumption to 95% throughout the dataset sample and upgraded the performance of the sensory network by about 19.5%. Thus, it prolonged the lifetime of the network.

Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.

The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.

The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

The purpose of this paper is to propose an optimal predictive model for the short-term forecast of real-time non-stationary machine variables by combining time series prediction with adaptive algorithms to minimize the error and to improve the prediction accuracy.

The proposed model is applied for prediction of speed and controller set point of three-phase induction motor operating on closed loop speed control with AC drive and PI controller. At Stage 1, the trend of the machine variables has been extracted and added to auto-regressive moving average (ARMA) time series prediction. ARMA prediction has been carried out using different combinations of AR and MA methods in order to make prediction with less Mean Squared Error (MSE).

The prediction error indicates the inadequacy of the model to estimate the data characteristics, which has been resolved at the subsequent stage by cascading an adaptive least mean square finite impulse response filter to the time series model. The adaptive filter receives the predicted output including training data and iteratively adjusts its coefficients for zero error convergence.

The componentized data prediction based on time series and cascade adaptive filter algorithm decomposes the non-stationary data characteristics for predictive maintenance. Evaluation of the model with different combination of time series algorithms and parameter settings of adaptive filter has been carried out to illustrate the performance of the prediction model. This prediction accuracy is compared with existing linear adaptive filter prediction using MSE as comparison index. The wide margin in the MSE values substantiates the prediction efficiency of the proposed model for machine data.

This model predicts the dynamic machine data with component decomposition at high accuracy, which enables to interpret the system response under dynamic conditions efficiently.

Filter design plays an essential role in most communication standards. The essential element of the software-defined radio is a channelizer that comprises several channel filters. Designing filters with lower complexity, minimized area and enhanced speed is a demanding task in currently prevailing communication standards. This study aims to propose an efficient reconfigurable residue number system (RNS)-based multiply-accumulate (MAC) channel filter for software radio receivers.

RNS-based pipelined MAC module for the realization of channel finite impulse response (FIR) filter architecture is considered in this work. Further, the use of a single adder and single multiplier for realizing the filter architecture regardless of the number of taps offers effective resource sharing. This design provides significant improvement in speed of operation as well as a reduction in area complexity.

In this paper, two major tasks have been considered: first, the RNS number conversion is performed in which the integer is converted into several residues. These residues are processed in parallel and are applied to the MAC-FIR filter architecture. Second, the MAC filter architecture involves pipelining, which enhances the speed of operation to a significant extent. Also, the time-sharing-based design incorporates a single partial product-based shift and add multiplier and single adder, which provide a low complex design. The results show that the proposed 16-tap RNS-based pipelined MAC sub-filter achieves significant improvement in speed as well as 89.87% area optimization when examined with the conventional RNS-based FIR filter structure.

The proposed MAC-FIR filter architecture provides good performance in terms of complexity and speed of operation because of the use of the RNS scheme with pipelining and partial product-based shift and adds multiplier and single adder when examining with the conventional designs. The reported architecture can be used in software radios.

Very large-scale integration (VLSI) digital signal processing became very popular and is predominantly used in several emerging applications. The optimal design of multirate filter with improvement in performance parameters such as less area, high speed and less power is the challenging task in most of the signal processing applications. This study aims to propose several effective multirate filter structures to accomplish sampling rate conversion.

The multirate filter structures considered in this work are polyphase filter and coefficient symmetry-based finite impulse response filter. The symmetry scheme particularly brings down the complexity to significant extent. To bring improvement in speed, delay registers are inserted at appropriate path with the help of pipelining and retiming scheme.

In this paper, the three tasks have been considered. First, the polyphase coefficient symmetry and modified polyphase (MP) structure is designed. Second, the pipelining is applied to the polyphase structure and the obtained results are compared with the polyphase structure. In third, retiming is applied to the polyphase structure and the performance comparison is carried out. The structures are realized for various orders, and the comparative analysis is carried out with the filter order N = 12, 30, 42, 8, 11 and 24 and the results are stated. The performance of all the accomplished structures is analyzed using Altera Quartus with the family cyclone II, device EP2C70F672C6. The results show that the multirate filter using pipelining and retiming offers better performance when examining with the conventional structures. Retimed and pipelined MP structure achieves a speed enhancement of about 33.81% when examining with the conventional polyphase (CP) structure with retiming and pipelining for N = 24 and M = 5. Likewise, the 2/3 structure of pipelined coefficient symmetry approach offers area reduction of about 54.76% over 2/3 structure of pipelined polyphase approach for N = 30 with little reduction in power. The fine grain pipelined and retimed MP structure with N = 11 and M = 3 avails critical path delay reduction of about 28.15% when examining with the corresponding fine grain pipelined and retimed CP structure.

The proposed distinct structures offer better alternative to conventional structures because of the symmetric coefficients, performance enhancement using pipelining and retiming based rate conversion structures. The suggested structures can be used for achieving different rates in software radios.

The purpose of this paper is to construct a flux-controlled memcapacitor (MC) emulator without grounded restriction with the binary operation ability. The active first-order low-pass filter (LPF) and high-pass filter (HPF) circuits are constructed by replacing the capacitor with MC.

The output saturation of the active device is innovatively adopted to realize the binary operation of MC with two memcapacitance values. By applying the direct current control voltage together with the input signal, the memcapacitance can be controlled, and hence, cut-off frequency of the filters can be adjusted without changing the circuit structure.

Experiments and simulation results show that the new filter has good frequency selectivity. Both LPF and HPF can change the cut-off frequency by changing the positive and negative control voltage. The experimental and simulation results are in good agreement with the theoretical analysis, which proves the feasibility and validity of the emulator and the filters.

These MC emulators are simple and easy to physically fabricate, which have been increasingly used for experiment. It also provide an effective reference for device miniaturization and low power consumption.

The purpose of this paper is to analyze the convergence performance of Bessel beamformer, based on the design steps of least mean square (LMS) algorithm, can be named as Bessel LMS (BLMS) algorithm. Its performance is compared in adaptive environment with LMS in terms of two important performance parameters, namely; convergence and mean square error. The proposed BLMS algorithm is implemented on digital signal processor along with antenna array to make it smart in wireless sensor networks.

Convergence analysis is theoretically developed and verified through MatLab Software.

Theoretical model is verified through simulation and its results are shown in the provided table.

The theoretical model can obtain validation from well-known result of Wiener filter theory through principle of orthogonality.

The purpose of this paper is to improve the performance of control loop suffering from control valve stiction. Control valve stiction is considered as of one of the main causes of oscillation in process variables, which require performing costly unplanned maintenance and process shutdown. An adaptive solution to handle valve stiction while maintaining safety and quality until next planned maintenance is highly desirable to save considerable cost and effort.

This paper implements a new stiction compensation method built using adaptive inverse model techniques and intelligent control theories. Finite impulse response (FIR) model, which is known to be robust, as a compensator for stiction. The parameters of FIR model are tuned in an adaptive way using differential evolution (DE) technique. The performance of proposed method is compared with other two compensation techniques.

The new method showed excellent performance of the DE–FIR compensator compared to other dynamic inversion methods in terms of minimizing process variability, energy saving and valve stem aggressiveness.

The compensation ability for all compensators reduces with the increase of stiction severity, thus the over shoot case always shows the worst result. In future works, other optimization techniques will be explored to find the appropriate technique that can extend the FIR model size with smallest computation time that can improve the performance of the compensator in over shoot case. In addition, the estimation of the valve residual life based on the level of stiction and effort required by the controller should be considered.

The presented approach represents an original contribution to the literature. It performs stiction compensation without a need for a prior knowledge on the process or the valve models and guarantees a smooth control of the stem movement with a low control effort. The proposed approach differs from previous adaptive methods as it uses stable FIR models and DE to find the appropriate parameters of the inverse model and handle nonlinear behavior of stiction.

This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.

The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.

In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.

The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.