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This paper presents a prediction on the impact of technology scaling on phase‐locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase‐frequency detector (PFD)‐based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.

Analogue models were developed and Mentor Graphics VHDL‐AMS mixed‐signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.

A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.

The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi‐VDD, multi‐Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.

This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture.

The purpose of this paper is to improve the tracking performance of the carrier phase lock loop (PLL) in the strapdown inertial navigation system/global positioning system (SINS/GPS) integrated system with an innovative scheme of ultra‐tight integration.

First, providing the Doppler frequency for PLL using SINS velocity could enlarge the loop equivalent bandwidth and reduce the dynamic effect on the carrier loop. Meanwhile, lowering the filter bandwidth could increase the immunity to noise. Second, the relationships between the PLL and SINS errors have been analyzed, and then the PLL error model is established to eliminate the correlation between the pseudo‐range‐rate error and SINS velocity error. Third, the carrier frequency is regulated to improve the tracking accuracy, according to the error estimations of Kalman filter.

The innovative ultra‐tightly integrated system could not only enhance the anti‐jamming capability and the dynamic tracking performance of the tracking loops, but also improve the pseudo‐range‐rate measurements accuracy for the integrated filter.

This paper provides further study on the method of enhancing the carrier‐tracking performance and improving the integration mode in the ultra‐tightly integrated system based on the software‐defined GPS receiver.

The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach.

This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplified average model and will show that following this approach, there is a mismatch between their actual and desired transient performance. A new PLL design method is then proposed based on the DPM approach that allows the development of fourth-order DPM models. The small-signal eigenvalues analysis of the fourth-order DPM models is used to determine the control gains and the stability limits.

The DPM approach is proven to be useful for single-phase PLLs stability analysis and control parameters design. It has been successfully used to design the control parameters and to predict the PLL stability limits, which have been validated via simulation and experimental tests consisting of grid voltage sag, phase jump and frequency step change.

This paper has introduced the use of DPM approach for the purpose of single-phase PLL stability analysis and control design. The approach has enabled accurate control gains design and stability limits identification of single-phase PLLs.

The purpose of this paper is to derive a new method for the hydrophilic finishing of wool fabric.

A new biological catalyst, microbial transglutaminase (mTGase), was used to catalyze the grafting of ε‐poly‐L‐lysine (ε‐PLL) onto the wool fabric.

The K/S value, SEM morphology and DSC analysis proved that the grafting reaction occurred. The hydrophilic properties of the ε‐PLL‐grafted wool fabrics were studied. The results showed that the grafted ε‐PLL could increase the hydrophilicity, which was demonstrated in terms of the obvious shortening in the wetting time and the process of water absorption and moisture absorption. The grafted wool also achieved better antistatic property.

Future work could be focused on the application of this biological method on other protein fabric which was designed to change the performance.

The biological approach is safe, eco‐friendly and effective relative to the conventional methods.

The purpose of this study is to improve the control performance of wind energy conversion systems (WECSs) by proposing a new sensorless, robust control strategy based on a Smith predictor active disturbance rejection control (SP-ADRC) associated with a speed/position estimator.

The estimator consists of a sliding mode observer (SMO) in combination with a phase-locked loop (PLL) to estimate the permanent magnet synchronous generator (PMSG) rotor position and speed. At the same time, the SP-ADRC is applied to the speed control loop of the variable-speed WECS control system to adapt strongly to dynamic characteristics under parameter uncertainties and disturbances.

Numerical simulations are conducted to evaluate the speed tracking performances under various wind speed profiles. The results show that the proposed sensorless speed control improves the accuracy of rotor speed and position estimation and provides better power tracking performance than a regular ADRC controller under fast wind speed variations.

This paper offers a new approach for designing sensorless, robust control for PMSG-based WECSs.

A new sensorless, robust control is proposed to improve the stability and tracking performance of PMSG-based WECSs. The SP-ADRC control attenuates the effects of parameter uncertainties and disturbances and eliminates the time-delay impact. The sensorless control design based on SMO and PLL improves the accuracy of rotor speed estimation and reduces the chattering problem of traditional SMO. The obtained results support the theoretical findings.

The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

In this study, a highly sensitive and quantitative analysis method using surface-enhanced Raman scattering (SERS)-labeled immunoassay is adopted for bisphenol A bisphenol A (BPA) detection in water samples.

Primarily, an excellent SERS immuno-nanoprobe is prepared, which relays on Au/Ag core-shell nanoparticles tagged 4-mercaptobenzoic acid (4MBA) and labeled with specific antibody against BPA. Second, the coating antigen of 4,4-Bis(4-hydroxyphenol) valeric acid (BVA) coupling poly-L-lysine (PLL) conjugate (BVA-PLL) is fastened on the substrate. Based on competitive immunoassay, the antibody labeled on SERS immuno-nanoprobe will bind with the free BPA and BVA-PLL competitively.

A calibration curve was obtained by plotting the intensity of SERS signal of 4MBA at 1007 cm⁻¹ versus the concentration of BPA. The results indicated that the limit of detection (LOD) for BPA is 1 ng/mL and present a great capacity for higher sensitivity. Furthermore, the method was able to quantitatively detect BPA in water samples, which was validated by high performance liquid chromatography (HPLC).

The method was developed based on competitive immunoassay, and the conjugate (BVA-PLL) was chosen as the coating antigen. Au/Ag core-shell nanoparticles played as the SERS active substrate and were labeled with Raman reporter. The value of this paper is supplying a wide potential for analysis of target analytes in the environmental monitoring and food safety.

In the dispersed generation system, power electronic converters allow for coupling between energy sources and the power grid. The requirements of Transmission System Operators are difficult to meet when the share of distributed energy sources of the total energy balance increases. These requirements allow to increase penetration of distributed generation sources without compromising power system stability and reliability. Therefore, in addition to control of active or reactive power, as well as voltage and frequency stabilization, the modern power electronic converters should support power grid in dynamic states or in the presence of nonlinear distortions. The paper aims to discuss these issues.

The research methodology used in this paper is based on three steps: Mathematical modelling and simulation studies, Experiments on laboratory test stand, Analyzing obtained results, evaluating them and formulating the conclusions.

The authors identified two algorithms, αβ-Filter and Voltage Controlled Oscillator, which are able to successfully cope with notch distortions. Other algorithms, used previously for voltage dips, operate improperly when the voltage grid has notching disturbances. This work evaluates six different synchronization algorithms with respect to the abilities to deal with notching.

The paper presents results of the synchronization algorithms in the presence of nonlinear notching interference. These studies were performed using the original hardware-software power grid emulator, real-time d’Space platform and power electronic converter. This methodology allowed us to exactly and accurately evaluate synchronization performance methods in the presence of complex nonlinear phenomena in power grid and power electronic converter. The results demonstrated that the best algorithms were αβ – Filtering and Voltage Controlled Oscilator.

In this paper, different synchronization algorithms have been tested. These included the classical Phase Locked Loop with Synchronous Reference Frame as well as modified algorithms developed by the authors, which displayed high robustness with respect to the notching interference. During the tests, the previously developed original test rig was used, allowing software-hardware emulation of grid phenomena.

The purpose of this paper is to present a novel scheme of high‐dynamic global positioning system (GPS) software receiver in order to improve the capturing speed and trading accuracy of GPS receiver.

First, the beginning of C/A code can be found through the delay and multiply approach. To solve the problems of estimating a certain satellite's Doppler shift from the signals of several visible satellites, the “delay and accumulation unit” is put forward, and besides, performance of inertial navigation system‐assisted tracking loop in high‐dynamic circumstance is analysed by means of mathematical modelling and simulation experiments, whose results verified the validity of the proposed tracking scheme.

In this paper, the two‐dimension searching process in conventional acquisition scheme is transformed into two one‐dimension searching processes, thus improving the capturing speed.

This software receiver has only been verified by means of mathematical simulation, and the validity in hardware receiver is still obscured.

This paper presents a novel high‐dynamic GPS software receiver scheme, which can be seen as a reference of engineering application and simulation research.

The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research.

This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO.

The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs.

Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it.

The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications.

The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.