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Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process.

Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved.

The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW.

A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC.

The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society.

The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.

The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients.

The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches.

In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents.

The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

The purpose of the paper is to introduce the dynamic phasor modelling (DPM) approach for stability investigation and control design of single-phase phase-locked loops (PLLs). The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach.

This paper starts by investigating the performance of three commonly used PLL schemes: the inverse park-PLL, the second-order generalised integrators (SOGI)-frequency-locked loop and the enhanced-PLL, designed using the simplified average model and will show that following this approach, there is a mismatch between their actual and desired transient performance. A new PLL design method is then proposed based on the DPM approach that allows the development of fourth-order DPM models. The small-signal eigenvalues analysis of the fourth-order DPM models is used to determine the control gains and the stability limits.

The DPM approach is proven to be useful for single-phase PLLs stability analysis and control parameters design. It has been successfully used to design the control parameters and to predict the PLL stability limits, which have been validated via simulation and experimental tests consisting of grid voltage sag, phase jump and frequency step change.

This paper has introduced the use of DPM approach for the purpose of single-phase PLL stability analysis and control design. The approach has enabled accurate control gains design and stability limits identification of single-phase PLLs.

The purpose of this study is to eliminate voltage harmonics and instantly measure the positive sequence fundamental voltage during unbalanced grid conditions, the dual second-order generalized integrator-phase locked loop used in series hybrid filter structures is often used in grid synchronisation in three-phase networks. The preferred series active hybrid power filter simultaneously compensates for voltage balancing and current harmonics generated by non-linear loads.

This paper examines the use of renewable energy–based microgrid (MG) to support linear and non-linear loads. It is capable of synchronising with both the utility and the diesel generator unit. Power is transferred from the grid throughout a stable grid situation with minimum renewable energy generation and maximum load demand. It synchronises with diesel generator set to supply the load and form an AC MG during outages and minimum renewable power generation. In islanded and grid-connected mode, the voltage and power quality issues of the MG are controlled by static synchronous compensator and series hybrid filter.

Because of the presence of non-linear loads, reactive loads in the distribution system and the injection of wind power into the grid integrated system result power quality issues like current harmonics, voltage fluctuations, reactive power demand, etc.

The voltage at the load (linear and non-linear) is regulated, and the power factor and total harmonic distortions were improved with the help of the series hybrid filter.

Charge pump phase locked loops (CPPLLs) are nonlinear systems as a result of the nonlinear behavior of voltage-controlled oscillators (VCO). This paper aims to specify jitter generation of voltage controlled oscillator phase noise in CPPLLs, by considering approximated practical model for VCO.

CPPLL, in practice, shows nonlinear behavior, and usually in LC-VCOs, it follows second-degree polynomial function behavior. Therefore, the nonlinear differential equation of the system is obtained which shows the CPPLLs are a nonlinear system with memory, and that Volterra series expansion is useful for such systems.

In this paper, by considering approximated practical model for VCO, jitter generation of voltage controlled oscillator phase noise in CPPLLs is specified. Behavioral simulation is used to validate the analytical results. The results show a suitable agreement between analytical equations and simulation results.

The proposed method in this paper has two advantages over the conventional design and analysis methods. First, in contrast to an ideal CPPLL, in which the characteristic of the VCO’s output frequency based on the control voltage is linear, in the present paper, a nonlinear behavior was considered for this characteristic in accordance with the real situations. Besides, regarding the simulations in this paper, a behavior similar to the second-degree polynomial was considered, which caused the dependence of the produced jitter’s characteristic corner frequency on the jitter’s amplitude. Second, some new nonlinear differential equations were proposed for the system, which ensured the calculation of the produced jitter of the VCO phase noise in CPPLLs. The presented method is general enough to be used for designing the CPPLL.

In the dispersed generation system, power electronic converters allow for coupling between energy sources and the power grid. The requirements of Transmission System Operators are difficult to meet when the share of distributed energy sources of the total energy balance increases. These requirements allow to increase penetration of distributed generation sources without compromising power system stability and reliability. Therefore, in addition to control of active or reactive power, as well as voltage and frequency stabilization, the modern power electronic converters should support power grid in dynamic states or in the presence of nonlinear distortions. The paper aims to discuss these issues.

The research methodology used in this paper is based on three steps: Mathematical modelling and simulation studies, Experiments on laboratory test stand, Analyzing obtained results, evaluating them and formulating the conclusions.

The authors identified two algorithms, αβ-Filter and Voltage Controlled Oscillator, which are able to successfully cope with notch distortions. Other algorithms, used previously for voltage dips, operate improperly when the voltage grid has notching disturbances. This work evaluates six different synchronization algorithms with respect to the abilities to deal with notching.

The paper presents results of the synchronization algorithms in the presence of nonlinear notching interference. These studies were performed using the original hardware-software power grid emulator, real-time d’Space platform and power electronic converter. This methodology allowed us to exactly and accurately evaluate synchronization performance methods in the presence of complex nonlinear phenomena in power grid and power electronic converter. The results demonstrated that the best algorithms were αβ – Filtering and Voltage Controlled Oscilator.

In this paper, different synchronization algorithms have been tested. These included the classical Phase Locked Loop with Synchronous Reference Frame as well as modified algorithms developed by the authors, which displayed high robustness with respect to the notching interference. During the tests, the previously developed original test rig was used, allowing software-hardware emulation of grid phenomena.

The purpose of this study is to improve the control performance of wind energy conversion systems (WECSs) by proposing a new sensorless, robust control strategy based on a Smith predictor active disturbance rejection control (SP-ADRC) associated with a speed/position estimator.

The estimator consists of a sliding mode observer (SMO) in combination with a phase-locked loop (PLL) to estimate the permanent magnet synchronous generator (PMSG) rotor position and speed. At the same time, the SP-ADRC is applied to the speed control loop of the variable-speed WECS control system to adapt strongly to dynamic characteristics under parameter uncertainties and disturbances.

Numerical simulations are conducted to evaluate the speed tracking performances under various wind speed profiles. The results show that the proposed sensorless speed control improves the accuracy of rotor speed and position estimation and provides better power tracking performance than a regular ADRC controller under fast wind speed variations.

This paper offers a new approach for designing sensorless, robust control for PMSG-based WECSs.

A new sensorless, robust control is proposed to improve the stability and tracking performance of PMSG-based WECSs. The SP-ADRC control attenuates the effects of parameter uncertainties and disturbances and eliminates the time-delay impact. The sensorless control design based on SMO and PLL improves the accuracy of rotor speed estimation and reduces the chattering problem of traditional SMO. The obtained results support the theoretical findings.

This paper aims to provide detailed information on the dynamic model and closed‐loop control theory for a resonant accelerometer based on electrostatic stiffness, which is important for the design of this type of resonant accelerometer.

After analysing the principles of the resonant accelerometer based on electrostatic stiffness, a dynamic model was built. According to the requirements of the closed‐loop control, the control equations based on phase‐locked technology were also built for the system. With the help of the averaging method, the system behaviour was analysed, and the equilibrium for the vibration amplitude was achieved.

The theoretical analysis and simulation show that integral gain is critical to system stability. When it is larger than the critical point, the system stable time is shorter, but the frequency‐tracking process fluctuates; if it is smaller than the critical point, the system stable time is longer, and the frequency‐tracking process stabilizes a resonant accelerometer was fabricated with a bulk‐silicon‐dissolved process. With the above conclusions, the accelerometer was driven and tested with a sensitivity of 47 Hz/g for a single vibration beam.

The dynamic model and the control theory for the resonant accelerometer based on electrostatic stiffness were presented in this paper. The simulation and experiment results agree well with the theoretical analysis.

This paper presents a prediction on the impact of technology scaling on phase‐locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase‐frequency detector (PFD)‐based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.

Analogue models were developed and Mentor Graphics VHDL‐AMS mixed‐signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.

A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.

The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi‐VDD, multi‐Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.

This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture.

The purpose of this paper is to improve the tracking performance of the carrier phase lock loop (PLL) in the strapdown inertial navigation system/global positioning system (SINS/GPS) integrated system with an innovative scheme of ultra‐tight integration.

First, providing the Doppler frequency for PLL using SINS velocity could enlarge the loop equivalent bandwidth and reduce the dynamic effect on the carrier loop. Meanwhile, lowering the filter bandwidth could increase the immunity to noise. Second, the relationships between the PLL and SINS errors have been analyzed, and then the PLL error model is established to eliminate the correlation between the pseudo‐range‐rate error and SINS velocity error. Third, the carrier frequency is regulated to improve the tracking accuracy, according to the error estimations of Kalman filter.

The innovative ultra‐tightly integrated system could not only enhance the anti‐jamming capability and the dynamic tracking performance of the tracking loops, but also improve the pseudo‐range‐rate measurements accuracy for the integrated filter.

This paper provides further study on the method of enhancing the carrier‐tracking performance and improving the integration mode in the ultra‐tightly integrated system based on the software‐defined GPS receiver.