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The purpose of this paper is to design and implement a fully integrated low‐phase noise and large tuning range dual‐band LC voltage‐controlled oscillator (VCO) in 0.13 μm complementary metal oxide semiconductor (CMOS) technology.

Two parallel‐connected single‐band VCOs are designed to implement the proposed VCO. Adopting a simple and straight‐forward architecture, the dual‐band VCO is configured to operate at two frequency bands, which are from 1.48 GHz to 1.78 GHz and from 2.08 GHz to 2.45 GHz. A band selection circuit is designed to perform band selection process based on the controlling input signal.

The proposed VCO features phase noise of −104.7 dBc/Hz and −108.8 dBc/Hz at 1 MHz offset frequency for both low corner and high corner end of the low‐band operation. For high‐band operation, phase‐noise performance of −101.1 dBc/Hz and −110.4 dBc/Hz at 1 MHz offset frequency are achieved. The measured output power of the dual‐band VCO ranges from −8.4 dBm to −5.8 dBm and from −9.6 dBm to −8.0 dBm for low‐band and high‐band operation, respectively. It was also observed that the power differences between the fundamental spectrum and the nearby spurious tone range from −67.5 dBc to −47.7 dBc.

The paper is useful to both the academic and industrial fields since it promotes the concept of multi‐band or multi‐standard system which is currently in demand in the telecommunication industry.

The purpose of this work in designing a wideband ring voltage-controlled oscillator (VCO) based on programmable current topology. It occupies a very tiny area yet achieving a good phase noise performance, which is suitable to be implemented in cost-effective and wideband frequency synthesizers.

The tuning range and gain are improved by dividing the VCO tuning curve into multiple curves controlled by programmable current sources without introducing additional parasitic capacitance.

Fabricated in 130-nm standard complementary metal oxide semiconductor technology and occupying an area of 0.079 mm², the VCO is tunable from 2.05 to 4.19 GHz, with a tuning percentage of 68.5 per cent. The VCO measures a phase noise performance of −96.7 dBc/Hz at an offset of 1 MHz from a 4.19 GHz carrier while consuming an average current of 6.5 mA, achieving figure of merit (FoM) and FoM_T of −158.9 and −175.6 dBc/Hz, respectively.

The proposed design uses programmable current topology without introducing parasitic capacitance, hence achieving wideband operation. It also occupies a tiny area and achieves a good phase noise performance.

Charge pump phase locked loops (CPPLLs) are nonlinear systems as a result of the nonlinear behavior of voltage-controlled oscillators (VCO). This paper aims to specify jitter generation of voltage controlled oscillator phase noise in CPPLLs, by considering approximated practical model for VCO.

CPPLL, in practice, shows nonlinear behavior, and usually in LC-VCOs, it follows second-degree polynomial function behavior. Therefore, the nonlinear differential equation of the system is obtained which shows the CPPLLs are a nonlinear system with memory, and that Volterra series expansion is useful for such systems.

In this paper, by considering approximated practical model for VCO, jitter generation of voltage controlled oscillator phase noise in CPPLLs is specified. Behavioral simulation is used to validate the analytical results. The results show a suitable agreement between analytical equations and simulation results.

The proposed method in this paper has two advantages over the conventional design and analysis methods. First, in contrast to an ideal CPPLL, in which the characteristic of the VCO’s output frequency based on the control voltage is linear, in the present paper, a nonlinear behavior was considered for this characteristic in accordance with the real situations. Besides, regarding the simulations in this paper, a behavior similar to the second-degree polynomial was considered, which caused the dependence of the produced jitter’s characteristic corner frequency on the jitter’s amplitude. Second, some new nonlinear differential equations were proposed for the system, which ensured the calculation of the produced jitter of the VCO phase noise in CPPLLs. The presented method is general enough to be used for designing the CPPLL.

The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.

First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.

This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm² compared to contemporary designs.

The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

The purpose of this paper is to design a low phase noise and high figure of merit, fully integrated, voltage‐controlled oscillator (VCO) which was fabricated in TSMC CMOS 0.18‐μm 1P6M process.

A differential PMOS cross‐coupled architecture VCO with the capacitive feedback technology was designed to increase the linearity of frequency tuning range and decrease the phase noise. Varactor determining the performance of tuning range is also a key component in the design of VCO. The authors adopt the accumulation‐mode MOS varactor. The output spectrum and the phase noise are measured by E5052A spectrum analyzer.

The VCO is successfully fabricated in TSMC RF CMOS 0.18um 1P6M process. The measured tuning range is from 10.875 GHz ∼ 11.1 GHz with control voltage from 0 to 1.5 V. The measured phase noise is as low as −120.42 dBc/Hz at 1 MHz offset and the high FOM is −189.5 dBc/Hz. The output spectrum is −10.51dBm with center oscillator frequency of 10.942 GHz. The core circuit without buffer consumes power of 15 mW from a 1.8 V supply voltage.

This paper shows a fully integrated CMOS LCVCO architecture using capacitive feedback technology with low phase noise and high figure of merit for OC‐192 SONET applications.

Multiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.

The proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.

The introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.

This technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

The paper aims to present the novel design approach for a low power LC-voltage-controlled oscillators (VCO) design with low phase noise that too targeted at the most sought band of Bluetooth applications. Owing to their crucial role in a wide variety of modern applications, VCO and phase-locked loop (PLL) frequency synthesizers have been the subject of extensive research in recent years. In fact, VCO is one of the key components being used in a modern PLL to provide local frequency signal since a few decades. The complicated synthesizer requirements imposed by cellular phone applications have been a key driver for PLL research.

This paper first opted to present the recent developments on implemented techniques of LC-VCO designs in popular RF bands. An LC-VCO with a differential (cross-coupled) MOS structure is then presented which has aimed to compensate the losses of an on-chip inductor implemented in UMC’s 130 nm RF-CMOS process. The LC-VCO is finally targeted to embed onto the synthesizer chip, to address the narrowband (S-Band) applications where Bluetooth has been the most sought one. The stacked inductor topology has been adopted to get the benefit of its on-chip compatibility and low noise. The active differential architecture, which basically is a cross-coupled NMOS structure, has been then envisaged for the gain which counters the losses completely. Three major areas of LC-VCO design are considered and worked upon for the optimum design parameters, which includes Bluetooth coverage range of 2.410 GHz to 2.490 GHz, better linearity and high sensitivity and finally the most sought phase noise performance for an LC-VCO.

The work provides the complete design aspect of a novel LC-VCO design for low phase noise narrowband applications such as Bluetooth. Using tuned MOS varactor, in 130 nm-RF CMOS process, a high gain sensitivity of 194 MHz/Volt was obtained. Thus, the entire frequency range of 2415-2500 MHz for Bluetooth applications, supporting multiple standards from 3G to 5G, was covered by voltage tuning of 0.7-1.0 V. To achieve the low power dissipation, low bias (1.2 V) cross-coupled differential structure was adopted, which completely paid for the losses occurred in the LC resonator. The power dissipation comes out to be 8.56 mW which is a remarkably small value for such a high gain and low noise VCO. For the VCO frequencies in the presented LO-plan, the tank inductor was allowed to have a moderate value of inductance (8 nH), while maintaining a very high Q factor. The LC-VCO of the proposed LO-generator achieved extremely low phase noise of −140 dBc/Hz @ 1 MHz, as compared to the contemporary designs.

Though a professional tool for inductor and circuit design (ADS-by Keysight Technologies) has been chosen, actual inductor and circuit implementation on silicon may still lead to various parasitic evolutions; therefore, one must have that margin pre-considered while finalizing the design and testing it.

The proposed LC-VCO architecture presented in this work shows low phase noise and wide tuning range with high gain sensitivity in S-Band, low power dissipation and narrowband nature of wireless applications.

The on-chip stacked inductor has uniquely been designed with the provided dimensions and other parameters. Though active design is in a conventional manner, its sizing and bias current selection are unique. The pool of results obtained completely preserves the originally to the full extent.

This paper aims to propose and demonstrate novel microphone sensors based on the frequency delta-sigma modulation (FDSM) technique, which replaces the conventional delta-sigma modulator in the delta-sigma analog-to digital converters. A key of the FDSM technology is to use a voltage-controlled oscillator (VCO) for converting an input analog signal to a 1-bit pulse-density modulated digital signal. High-performance sensors can be realized if the VCO is replaced by an oscillator whose oscillation frequency depends on an external physical parameter.

Microphone sensors are proposed based on FDSM that uses a suspended microstrip disk resonator, where the backside ground plane is replaced by a thin metal diaphragm. A resonant tunneling diode (RTD) oscillator is also used, as the performance of these sensors significantly depends on the oscillation frequency. To demonstrate the basic operation of the proposal, prototype devices were fabricated with an InGaAs/AlAs RTD.

A satisfactory noise shaping property, which is a significant nature of delta-sigma modulation, was demonstrated over three decades for the prototype device. A sound-sensing peak was also clearly observed when applying 1 kHz sound from a speaker.

High-performance ultrasonic microphone sensors can be realized if the sensors are fabricated by using a thin InP substrate with high-frequency oscillator design.

In this study, the authors proposed and experimentally demonstrated novel microphone sensors, which are promising as future ultrasonic sensors that have high dynamic range with wide bandwidth.

The demand for higher bandwidth has resulted in the development of mm-wave phased array systems. This paper aims to explore a technique that could be used to feed the individual antennas in a mm-wave phased array system with the appropriate phase shifted signal to achieve the required directivity. It presents differential Colpitts oscillators at 5 and 60 GHz that can provide differential output signals to the quadrature signal generators in the proposed phase shifter system.

The phase shifter system comprises a differential Colpitts voltage controlled oscillator (VCO) and utilizes the vector-sum technique to generate the phase shifted signal. The differential VCO is connected in the common-collector configuration for the 5-GHz VCO, and is extended using a cascode transistor for the 60-GHz VCO for better stability at mm-wave. The vector sum is achieved using a variable gain amplifier (VGA) that combines the in-phase and quadrature phase signal, generated from oscillator output using hybrid Lange couplers. The devices were fabricated using IBM 130-nm SiGe BiCMOS process, and simulations were performed with a process design kit provided by the foundry.

The measured results of the 5-GHz and 60-GHz VCOs indicate that differential Colpitts VCO could generate oscillator output with good phase noise performance. The simulation results of the phase shifter system indicate that the generation of signals with phases from 0° to 360° in steps of 22.5° was achieved using the proposed approach. A Gilbert mixer topology was used for the VGA and the linearity was improved by a pre-distortion circuit implemented using an inverse tanh cell.

The measurement results indicate that differential Colpitts oscillator in common-collector configuration could be used to generate differential VCO signals for the vector-sum phase shifter. The simulation results of the proposed phase shifter system at mm-wave show that the phase shift could be realised at a total power consumption of 200 mW.

In the dispersed generation system, power electronic converters allow for coupling between energy sources and the power grid. The requirements of Transmission System Operators are difficult to meet when the share of distributed energy sources of the total energy balance increases. These requirements allow to increase penetration of distributed generation sources without compromising power system stability and reliability. Therefore, in addition to control of active or reactive power, as well as voltage and frequency stabilization, the modern power electronic converters should support power grid in dynamic states or in the presence of nonlinear distortions. The paper aims to discuss these issues.

The research methodology used in this paper is based on three steps: Mathematical modelling and simulation studies, Experiments on laboratory test stand, Analyzing obtained results, evaluating them and formulating the conclusions.

The authors identified two algorithms, αβ-Filter and Voltage Controlled Oscillator, which are able to successfully cope with notch distortions. Other algorithms, used previously for voltage dips, operate improperly when the voltage grid has notching disturbances. This work evaluates six different synchronization algorithms with respect to the abilities to deal with notching.

The paper presents results of the synchronization algorithms in the presence of nonlinear notching interference. These studies were performed using the original hardware-software power grid emulator, real-time d’Space platform and power electronic converter. This methodology allowed us to exactly and accurately evaluate synchronization performance methods in the presence of complex nonlinear phenomena in power grid and power electronic converter. The results demonstrated that the best algorithms were αβ – Filtering and Voltage Controlled Oscilator.

In this paper, different synchronization algorithms have been tested. These included the classical Phase Locked Loop with Synchronous Reference Frame as well as modified algorithms developed by the authors, which displayed high robustness with respect to the notching interference. During the tests, the previously developed original test rig was used, allowing software-hardware emulation of grid phenomena.